[RISCV] Prevent copying dummy_reg_pair_with_x0 in RISCVMakeCompressible.

Author: topperc

llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp

@@ -452,13 +452,21 @@ bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
             .addReg(RegImm.Reg);
       } else if (RISCV::GPRPairRegClass.contains(RegImm.Reg)) {
         assert(RegImm.Imm == 0);
+        MCRegister EvenReg = TRI.getSubReg(RegImm.Reg, RISCV::sub_gpr_even);
+        MCRegister OddReg;
+        // We need to special case odd reg for X0_PAIR.
+        if (RegImm.Reg == RISCV::X0_Pair)
+          OddReg = RISCV::X0;
+        else
+          OddReg = TRI.getSubReg(RegImm.Reg, RISCV::sub_gpr_odd);
+        assert(NewReg != RISCV::X0_Pair && "Cannot write to X0_Pair");
         BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::ADDI),
                 TRI.getSubReg(NewReg, RISCV::sub_gpr_even))
-            .addReg(TRI.getSubReg(RegImm.Reg, RISCV::sub_gpr_even))
+            .addReg(EvenReg)
             .addImm(0);
         BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::ADDI),
                 TRI.getSubReg(NewReg, RISCV::sub_gpr_odd))
-            .addReg(TRI.getSubReg(RegImm.Reg, RISCV::sub_gpr_odd))
+            .addReg(OddReg)
             .addImm(0);
       } else {
         assert((RISCV::FPR32RegClass.contains(RegImm.Reg) ||

llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir

@@ -137,7 +137,7 @@ body:             |
     ; RV32: liveins: $x10, $x11, $x12
     ; RV32-NEXT: {{  $}}
     ; RV32-NEXT: $x14 = ADDI $x0, 0
-    ; RV32-NEXT: $x15 = ADDI $dummy_reg_pair_with_x0, 0
+    ; RV32-NEXT: $x15 = ADDI $x0, 0
     ; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a)
     ; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b)
     ; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c)