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[PowerPC] Combine sub within setcc back to sext
1 parent 71eda17 commit d91592a

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2 files changed

+72
-39
lines changed

2 files changed

+72
-39
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 50 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14527,15 +14527,18 @@ SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
1452714527
ShiftCst);
1452814528
}
1452914529

14530-
SDValue PPCTargetLowering::combineSetCC(SDNode *N,
14531-
DAGCombinerInfo &DCI) const {
14532-
assert(N->getOpcode() == ISD::SETCC &&
14533-
"Should be called with a SETCC node");
14530+
SDValue PPCTargetLowering::combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const {
14531+
assert(N->getOpcode() == ISD::SETCC && "Should be called with a SETCC node");
1453414532

1453514533
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
14534+
SDValue LHS = N->getOperand(0);
14535+
SDValue RHS = N->getOperand(1);
14536+
SDLoc DL(N);
14537+
SelectionDAG &DAG = DCI.DAG;
14538+
EVT VT = N->getValueType(0);
14539+
EVT OpVT = LHS.getValueType();
14540+
1453614541
if (CC == ISD::SETNE || CC == ISD::SETEQ) {
14537-
SDValue LHS = N->getOperand(0);
14538-
SDValue RHS = N->getOperand(1);
1453914542

1454014543
// If there is a '0 - y' pattern, canonicalize the pattern to the RHS.
1454114544
if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
@@ -14546,15 +14549,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
1454614549
// x != 0-y --> x+y != 0
1454714550
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
1454814551
RHS.hasOneUse()) {
14549-
SDLoc DL(N);
14550-
SelectionDAG &DAG = DCI.DAG;
14551-
EVT VT = N->getValueType(0);
14552-
EVT OpVT = LHS.getValueType();
1455314552
SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
1455414553
return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
1455514554
}
1455614555
}
1455714556

14557+
if (CC == ISD::SETULT && isa<ConstantSDNode>(RHS)) {
14558+
uint64_t RHSVal = cast<ConstantSDNode>(RHS)->getZExtValue();
14559+
if (LHS.getOpcode() == ISD::ADD && isa<ConstantSDNode>(LHS.getOperand(1))) {
14560+
uint64_t Addend = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
14561+
if (OpVT == MVT::i64) {
14562+
uint64_t ShiftVal = ~Addend + 1;
14563+
uint64_t CmpVal = ~RHSVal + 1;
14564+
if (isPowerOf2_64(ShiftVal) && ShiftVal << 1 == CmpVal) {
14565+
unsigned DestBits = Log2_64(CmpVal);
14566+
if (DestBits == 8 || DestBits == 16 || DestBits == 32) {
14567+
SDValue Conv = DAG.getSExtOrTrunc(
14568+
DAG.getSExtOrTrunc(LHS.getOperand(0), DL,
14569+
MVT::getIntegerVT(DestBits)),
14570+
DL, OpVT);
14571+
return DAG.getSetCC(DL, VT, LHS.getOperand(0), Conv, ISD::SETNE);
14572+
}
14573+
}
14574+
} else if (OpVT == MVT::i32) {
14575+
if (RHSVal == 0xffffff00 && Addend == 0xffffff80) {
14576+
SDValue Conv = DAG.getSExtOrTrunc(
14577+
DAG.getSExtOrTrunc(LHS.getOperand(0), DL, MVT::i8), DL, OpVT);
14578+
return DAG.getSetCC(DL, VT, LHS.getOperand(0), Conv, ISD::SETNE);
14579+
}
14580+
}
14581+
} else if (LHS.getOpcode() == ISD::SRL &&
14582+
LHS.getOperand(0).getOpcode() == ISD::ADD &&
14583+
isa<ConstantSDNode>(LHS.getOperand(1)) &&
14584+
isa<ConstantSDNode>(LHS.getOperand(0).getOperand(1))) {
14585+
if (RHSVal == 0xffff &&
14586+
cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 16 &&
14587+
cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))
14588+
->getZExtValue() == 0xffff8000) {
14589+
SDValue Conv = DAG.getSExtOrTrunc(
14590+
DAG.getSExtOrTrunc(LHS.getOperand(0).getOperand(0), DL, MVT::i16),
14591+
DL, OpVT);
14592+
return DAG.getSetCC(DL, VT, LHS.getOperand(0).getOperand(0), Conv,
14593+
ISD::SETNE);
14594+
}
14595+
}
14596+
}
14597+
1455814598
return DAGCombineTruncBoolExt(N, DCI);
1455914599
}
1456014600

‎llvm/test/CodeGen/PowerPC/setcc-to-sub.ll‎

Lines changed: 22 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -92,12 +92,10 @@ entry:
9292
define zeroext i1 @test5(i64 %a) {
9393
; CHECK-LABEL: test5:
9494
; CHECK: # %bb.0: # %entry
95-
; CHECK-NEXT: li 4, -1
96-
; CHECK-NEXT: addis 3, 3, -32768
97-
; CHECK-NEXT: rldic 4, 4, 32, 0
98-
; CHECK-NEXT: subc 4, 3, 4
99-
; CHECK-NEXT: subfe 3, 3, 3
100-
; CHECK-NEXT: neg 3, 3
95+
; CHECK-NEXT: extsw 4, 3
96+
; CHECK-NEXT: xor 3, 3, 4
97+
; CHECK-NEXT: addic 4, 3, -1
98+
; CHECK-NEXT: subfe 3, 4, 3
10199
; CHECK-NEXT: blr
102100
entry:
103101
%0 = add i64 %a, -2147483648
@@ -108,11 +106,10 @@ entry:
108106
define zeroext i1 @test6(i64 %a) {
109107
; CHECK-LABEL: test6:
110108
; CHECK: # %bb.0: # %entry
111-
; CHECK-NEXT: addi 3, 3, -32768
112-
; CHECK-NEXT: lis 4, -1
113-
; CHECK-NEXT: subc 4, 3, 4
114-
; CHECK-NEXT: subfe 3, 3, 3
115-
; CHECK-NEXT: neg 3, 3
109+
; CHECK-NEXT: extsh 4, 3
110+
; CHECK-NEXT: xor 3, 3, 4
111+
; CHECK-NEXT: addic 4, 3, -1
112+
; CHECK-NEXT: subfe 3, 4, 3
116113
; CHECK-NEXT: blr
117114
entry:
118115
%0 = add i64 %a, -32768
@@ -123,11 +120,10 @@ entry:
123120
define zeroext i1 @test7(i64 %a) {
124121
; CHECK-LABEL: test7:
125122
; CHECK: # %bb.0: # %entry
126-
; CHECK-NEXT: addi 3, 3, -128
127-
; CHECK-NEXT: li 4, -256
128-
; CHECK-NEXT: subc 4, 3, 4
129-
; CHECK-NEXT: subfe 3, 3, 3
130-
; CHECK-NEXT: neg 3, 3
123+
; CHECK-NEXT: extsb 4, 3
124+
; CHECK-NEXT: xor 3, 3, 4
125+
; CHECK-NEXT: addic 4, 3, -1
126+
; CHECK-NEXT: subfe 3, 4, 3
131127
; CHECK-NEXT: blr
132128
entry:
133129
%0 = add i64 %a, -128
@@ -138,12 +134,11 @@ entry:
138134
define zeroext i1 @test8(i32 %a) {
139135
; CHECK-LABEL: test8:
140136
; CHECK: # %bb.0: # %entry
141-
; CHECK-NEXT: addi 3, 3, -32768
142-
; CHECK-NEXT: lis 4, -1
143-
; CHECK-NEXT: rlwinm 3, 3, 16, 16, 31
144-
; CHECK-NEXT: ori 4, 4, 1
145-
; CHECK-NEXT: add 3, 3, 4
146-
; CHECK-NEXT: rldicl 3, 3, 1, 63
137+
; CHECK-NEXT: extsh 4, 3
138+
; CHECK-NEXT: xor 3, 3, 4
139+
; CHECK-NEXT: cntlzw 3, 3
140+
; CHECK-NEXT: srwi 3, 3, 5
141+
; CHECK-NEXT: xori 3, 3, 1
147142
; CHECK-NEXT: blr
148143
entry:
149144
%0 = add i32 %a, -32768
@@ -154,13 +149,11 @@ entry:
154149
define zeroext i1 @test9(i32 %a) {
155150
; CHECK-LABEL: test9:
156151
; CHECK: # %bb.0: # %entry
157-
; CHECK-NEXT: lis 4, -256
158-
; CHECK-NEXT: addi 3, 3, -128
159-
; CHECK-NEXT: ori 4, 4, 1
160-
; CHECK-NEXT: clrldi 3, 3, 32
161-
; CHECK-NEXT: rldic 4, 4, 8, 0
162-
; CHECK-NEXT: add 3, 3, 4
163-
; CHECK-NEXT: rldicl 3, 3, 1, 63
152+
; CHECK-NEXT: extsb 4, 3
153+
; CHECK-NEXT: xor 3, 3, 4
154+
; CHECK-NEXT: cntlzw 3, 3
155+
; CHECK-NEXT: srwi 3, 3, 5
156+
; CHECK-NEXT: xori 3, 3, 1
164157
; CHECK-NEXT: blr
165158
entry:
166159
%0 = add i32 %a, -128

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