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author
Thorsten Schütt
committed
address review comments
1 parent d654ee9 commit d9baace

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8 files changed

+34
-24
lines changed

8 files changed

+34
-24
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -925,7 +925,7 @@ class CombinerHelper {
925925
bool matchUnmergeValuesAnyExtBuildVector(const MachineInstr &MI,
926926
BuildFnTy &MatchInfo);
927927

928-
// merge_values(_, undef) -> zext
928+
// merge_values(_, undef) -> anyext
929929
bool matchMergeXAndUndef(const MachineInstr &MI, BuildFnTy &MatchInfo);
930930

931931
private:

‎llvm/include/llvm/Target/GlobalISel/Combine.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -420,7 +420,7 @@ def binop_right_undef_to_undef: GICombineRule<
420420

421421
def unary_undef_to_zero: GICombineRule<
422422
(defs root:$root),
423-
(match (wip_match_opcode G_ABS, G_ZEXT):$root,
423+
(match (wip_match_opcode G_ABS):$root,
424424
[{ return Helper.matchOperandIsUndef(*${root}, 1); }]),
425425
(apply [{ Helper.replaceInstWithConstant(*${root}, 0); }])>;
426426

@@ -856,7 +856,7 @@ def unmerge_zext_to_zext : GICombineRule<
856856
(apply [{ Helper.applyCombineUnmergeZExtToZExt(*${d}); }])
857857
>;
858858

859-
/// Transform merge_x_undef -> zext.
859+
/// Transform merge_x_undef -> anyext.
860860
def merge_of_x_and_undef : GICombineRule <
861861
(defs root:$root, build_fn_matchinfo:$matchinfo),
862862
(match (G_IMPLICIT_DEF $undef),

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2944,11 +2944,8 @@ void CombinerHelper::replaceInstWithFConstant(MachineInstr &MI, double C) {
29442944

29452945
void CombinerHelper::replaceInstWithConstant(MachineInstr &MI, int64_t C) {
29462946
assert(MI.getNumDefs() == 1 && "Expected only one def?");
2947-
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2948-
if (isLegalOrBeforeLegalizer({TargetOpcode::G_CONSTANT, {DstTy}})) {
2949-
Builder.buildConstant(MI.getOperand(0), C);
2950-
MI.eraseFromParent();
2951-
}
2947+
Builder.buildConstant(MI.getOperand(0), C);
2948+
MI.eraseFromParent();
29522949
}
29532950

29542951
void CombinerHelper::replaceInstWithConstant(MachineInstr &MI, APInt C) {

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -535,7 +535,7 @@ body: |
535535
$q1 = COPY %un2(s128)
536536
...
537537

538-
# Check that we zext the merge
538+
# Check that we anyext the merge
539539
---
540540
name: test_merge_undef
541541
body: |
@@ -550,7 +550,7 @@ body: |
550550
$q0 = COPY %me(s128)
551551
...
552552

553-
# Check that we don't zext the merge, multi-use
553+
# Check that we don't anyext the merge, multi-use
554554
---
555555
name: test_merge_undef_multi_use
556556
body: |

‎llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -322,18 +322,17 @@ define void @typei1_orig(i64 %a, ptr %p, ptr %q) {
322322
;
323323
; CHECK-GI-LABEL: typei1_orig:
324324
; CHECK-GI: // %bb.0:
325-
; CHECK-GI-NEXT: ldr q0, [x2]
325+
; CHECK-GI-NEXT: ldr q1, [x2]
326326
; CHECK-GI-NEXT: cmp x0, #0
327+
; CHECK-GI-NEXT: movi v0.2d, #0xffffffffffffffff
327328
; CHECK-GI-NEXT: cset w8, gt
328-
; CHECK-GI-NEXT: neg v0.8h, v0.8h
329-
; CHECK-GI-NEXT: dup v1.8h, w8
330-
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
331-
; CHECK-GI-NEXT: mul v1.8h, v0.8h, v1.8h
332-
; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, #0
329+
; CHECK-GI-NEXT: neg v1.8h, v1.8h
330+
; CHECK-GI-NEXT: dup v2.8h, w8
333331
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
332+
; CHECK-GI-NEXT: mul v1.8h, v1.8h, v2.8h
334333
; CHECK-GI-NEXT: cmeq v1.8h, v1.8h, #0
335334
; CHECK-GI-NEXT: mvn v1.16b, v1.16b
336-
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
335+
; CHECK-GI-NEXT: uzp1 v0.16b, v1.16b, v0.16b
337336
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
338337
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
339338
; CHECK-GI-NEXT: str q0, [x1]

‎llvm/test/CodeGen/AArch64/extract-vector-elt.ll‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,17 @@
88
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v4i32_vector_extract_const
99

1010
define i64 @extract_v2i64_undef_index(<2 x i64> %a, i32 %c) {
11-
; CHECK-LABEL: extract_v2i64_undef_index:
12-
; CHECK: // %bb.0: // %entry
13-
; CHECK-NEXT: fmov x0, d0
14-
; CHECK-NEXT: ret
11+
; CHECK-SD-LABEL: extract_v2i64_undef_index:
12+
; CHECK-SD: // %bb.0: // %entry
13+
; CHECK-SD-NEXT: fmov x0, d0
14+
; CHECK-SD-NEXT: ret
15+
;
16+
; CHECK-GI-LABEL: extract_v2i64_undef_index:
17+
; CHECK-GI: // %bb.0: // %entry
18+
; CHECK-GI-NEXT: str q0, [sp, #-16]!
19+
; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
20+
; CHECK-GI-NEXT: ldr x0, [sp], #16
21+
; CHECK-GI-NEXT: ret
1522
entry:
1623
%d = extractelement <2 x i64> %a, i32 undef
1724
ret i64 %d

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -261,7 +261,8 @@ body: |
261261
; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_16
262262
; CHECK: liveins: $vgpr0
263263
; CHECK-NEXT: {{ $}}
264-
; CHECK-NEXT: %zext:_(s32) = G_CONSTANT i32 0
264+
; CHECK-NEXT: %shift:_(s16) = G_IMPLICIT_DEF
265+
; CHECK-NEXT: %zext:_(s32) = G_ZEXT %shift(s16)
265266
; CHECK-NEXT: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
266267
; CHECK-NEXT: $vgpr0 = COPY %result(s32)
267268
%arg:_(s32) = COPY $vgpr0
@@ -283,7 +284,8 @@ body: |
283284
; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_24
284285
; CHECK: liveins: $vgpr0
285286
; CHECK-NEXT: {{ $}}
286-
; CHECK-NEXT: %zext:_(s32) = G_CONSTANT i32 0
287+
; CHECK-NEXT: %shift:_(s16) = G_IMPLICIT_DEF
288+
; CHECK-NEXT: %zext:_(s32) = G_ZEXT %shift(s16)
287289
; CHECK-NEXT: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
288290
; CHECK-NEXT: $vgpr0 = COPY %result(s32)
289291
%arg:_(s32) = COPY $vgpr0

‎llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4074,12 +4074,14 @@ define amdgpu_kernel void @v_test_v2i16_x_add_undef_neg32(ptr addrspace(1) %out,
40744074
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
40754075
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
40764076
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
4077-
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
40784077
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
40794078
; VI-GISEL-NEXT: v_not_b32_e32 v2, 31
4079+
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
4080+
; VI-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
40804081
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
40814082
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
40824083
; VI-GISEL-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
4084+
; VI-GISEL-NEXT: v_or_b32_e32 v2, s0, v2
40834085
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
40844086
; VI-GISEL-NEXT: s_endpgm
40854087
;
@@ -4189,12 +4191,15 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg32_undef(ptr addrspace(1) %out,
41894191
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
41904192
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
41914193
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
4194+
; VI-GISEL-NEXT: s_and_b32 s2, 0xffff, s0
41924195
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
41934196
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
41944197
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
4198+
; VI-GISEL-NEXT: s_lshl_b32 s0, s2, 16
41954199
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
41964200
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
41974201
; VI-GISEL-NEXT: v_add_u16_e32 v2, 0xffe0, v3
4202+
; VI-GISEL-NEXT: v_or_b32_e32 v2, s0, v2
41984203
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
41994204
; VI-GISEL-NEXT: s_endpgm
42004205
;

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