Simplify

Author: MacDue

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -2577,13 +2577,9 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
               AFI->getCalleeSaveBaseToFrameRecordOffset()) {
         // If we have have an non-zero offset to the non-SVE CS base we need to
         // compute the base address by subtracting the offest in a temporary
-        // register. SVE functions have a "big stack" so there should be at
-        // least one scratch register available.
-        RegScavenger RS;
-        RS.enterBasicBlockEnd(MBB);
-        RS.backward(MBBI);
-        CalleeSaveBase = RS.FindUnusedReg(&AArch64::GPR64commonRegClass);
-        assert(CalleeSaveBase != AArch64::NoRegister);
+        // register first (to avoid briefly deallocating the SVE CS).
+        CalleeSaveBase = MBB.getParent()->getRegInfo().createVirtualRegister(
+            &AArch64::GPR64RegClass);
         emitFrameOffset(MBB, RestoreBegin, DL, CalleeSaveBase, AArch64::FP,
                         StackOffset::getFixed(-CalleeSaveBaseOffset), TII,
                         MachineInstr::FrameDestroy);

llvm/test/CodeGen/AArch64/stack-hazard.ll

@@ -3771,8 +3771,8 @@ define i32 @svecc_call_realign(<4 x i16> %P0, i32 %P1, i32 %P2, <vscale x 16 x i
 ; CHECK64-NEXT:    mov w0, #22647 // =0x5877
 ; CHECK64-NEXT:    movk w0, #59491, lsl #16
 ; CHECK64-NEXT:    .cfi_restore vg
-; CHECK64-NEXT:    sub x1, x29, #64
-; CHECK64-NEXT:    addvl sp, x1, #-18
+; CHECK64-NEXT:    sub x8, x29, #64
+; CHECK64-NEXT:    addvl sp, x8, #-18
 ; CHECK64-NEXT:    ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
 ; CHECK64-NEXT:    ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
 ; CHECK64-NEXT:    ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
@@ -3903,8 +3903,8 @@ define i32 @svecc_call_realign(<4 x i16> %P0, i32 %P1, i32 %P2, <vscale x 16 x i
 ; CHECK1024-NEXT:    mov w0, #22647 // =0x5877
 ; CHECK1024-NEXT:    movk w0, #59491, lsl #16
 ; CHECK1024-NEXT:    .cfi_restore vg
-; CHECK1024-NEXT:    sub x1, x29, #1024
-; CHECK1024-NEXT:    addvl sp, x1, #-18
+; CHECK1024-NEXT:    sub x8, x29, #1024
+; CHECK1024-NEXT:    addvl sp, x8, #-18
 ; CHECK1024-NEXT:    ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
 ; CHECK1024-NEXT:    ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
 ; CHECK1024-NEXT:    ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload