[RISCV] Add NoStdExtZfa predicates to BuildPairF64Pseudo and SplitF64Pseudo.

The makes the priority of the Zfa patterns of the pseudos explicit.
Previously the priority only worked because instructions with
usesCustomInserter=1 have lower priority.

Author: topperc

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -316,6 +316,7 @@ def FeatureStdExtZfa
 def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
                    AssemblerPredicate<(all_of FeatureStdExtZfa),
                                       "'Zfa' (Additional Floating-Point)">;
+def NoStdExtZfa : Predicate<"!Subtarget->hasStdExtZfa()">;
 
 def FeatureStdExtZfinx
     : RISCVExtension<1, 0, "Float in Integer", [FeatureStdExtZicsr]>;

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

@@ -488,7 +488,9 @@ def : LdPat<load, FLD, f64>;
 /// Stores
 
 def : StPat<store, FSD, FPR64, f64>;
+} // Predicates = [HasStdExtD]
 
+let Predicates = [HasStdExtD, NoStdExtZfa, IsRV32] in {
 /// Pseudo-instructions needed for the soft-float ABI with RV32D
 
 // Moves two GPRs to an FPR.
@@ -503,7 +505,7 @@ def SplitF64Pseudo
     : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
              [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
 
-} // Predicates = [HasStdExtD]
+} // Predicates = [HasStdExtD, NoStdExtZfa, IsRV32]
 
 let Predicates = [HasStdExtZdinx, IsRV64] in {
 defm Select_FPR64INX : SelectCC_GPR_rrirr<FPR64INX, f64>;