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Test some cases with mixed sgpr and vgpr inputs
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‎llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir‎

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@@ -557,3 +557,174 @@ body: |
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S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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...
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---
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name: vreg_128_mixed_sgpr_vgpr_copy_sources_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr8, $sgpr9
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; CHECK-LABEL: name: vreg_128_mixed_sgpr_vgpr_copy_sources_0
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr8, $sgpr9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr8
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr9
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY4]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = COPY $vgpr1
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%2:sreg_32 = COPY $sgpr8
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%3:sreg_32 = COPY $sgpr9
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%4:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%5:areg_128 = COPY %4
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$agpr0_agpr1_agpr2_agpr3 = COPY %5
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S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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...
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---
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name: vreg_128_mixed_sgpr_vgpr_copy_sources_1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr8, $sgpr9, $sgpr10
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; CHECK-LABEL: name: vreg_128_mixed_sgpr_vgpr_copy_sources_1
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; CHECK: liveins: $vgpr0, $sgpr8, $sgpr9, $sgpr10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr10
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY4]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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%0:vgpr_32 = COPY $vgpr0
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%1:sreg_32 = COPY $sgpr8
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%2:sreg_32 = COPY $sgpr9
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%3:sreg_32 = COPY $sgpr10
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%4:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%5:areg_128 = COPY %4
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$agpr0_agpr1_agpr2_agpr3 = COPY %5
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S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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...
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---
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name: vreg_128_mixed_sgpr_vgpr_copy_sources_2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr8
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; CHECK-LABEL: name: vreg_128_mixed_sgpr_vgpr_copy_sources_2
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr8
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY4]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr2
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%3:sreg_32 = COPY $sgpr8
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%4:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%5:areg_128 = COPY %4
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$agpr0_agpr1_agpr2_agpr3 = COPY %5
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S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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...
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---
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name: vreg_128_mixed_sgpr_vgpr_imm_sources_0
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: vreg_128_mixed_sgpr_vgpr_imm_sources_0
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; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3
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; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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%0:sgpr_32 = S_MOV_B32 0
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%1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%2:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %0, %subreg.sub2, %1, %subreg.sub3
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%3:areg_128 = COPY %2
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$agpr0_agpr1_agpr2_agpr3 = COPY %3
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S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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...
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---
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name: vreg_128_mixed_sgpr_vgpr_imm_sources_1
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: vreg_128_mixed_sgpr_vgpr_imm_sources_1
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; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 999
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3
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; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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%0:sgpr_32 = S_MOV_B32 999
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%1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%2:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %0, %subreg.sub2, %1, %subreg.sub3
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%3:areg_128 = COPY %2
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$agpr0_agpr1_agpr2_agpr3 = COPY %3
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S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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...
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---
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name: vreg_128_mixed_sgpr_vgpr_imm_sources_2
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: vreg_128_mixed_sgpr_vgpr_imm_sources_2
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; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 999
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3
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; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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%0:sgpr_32 = S_MOV_B32 999
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%1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%2:vreg_128 = REG_SEQUENCE %1, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
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%3:areg_128 = COPY %2
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$agpr0_agpr1_agpr2_agpr3 = COPY %3
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S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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...
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---
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name: vreg_128_mixed_sgpr_vgpr_imm_sources_3
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: vreg_128_mixed_sgpr_vgpr_imm_sources_3
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; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 8
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3
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; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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%0:sgpr_32 = S_MOV_B32 8
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%1:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
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%2:vreg_128 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1, %1, %subreg.sub2, %0, %subreg.sub3
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%3:areg_128 = COPY %2
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$agpr0_agpr1_agpr2_agpr3 = COPY %3
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S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
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...

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