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[MISched] Unify the way to specify scheduling direction (#119518)
For pre-ra scheduling, we use two options `-misched-topdown` and `-misched-bottomup` to force the direction. While for post-ra scheduling, we use `-misched-postra-direction` with enumerated values (`topdown`, `bottomup` and `bidirectional`). This is not unified and adds some mental burdens. Here we replace these two options `-misched-topdown` and `-misched-bottomup` with `-misched-prera-direction` with the same enumerated values. To avoid the condition of `getNumOccurrences() > 0`, we add a new enum value `Unspecified` and make it the default initial value. These options are hidden, so we needn't keep the compatibility.
1 parent fd2f8d4 commit da71203

14 files changed

+70
-72
lines changed

‎llvm/include/llvm/CodeGen/MachineScheduler.h‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,8 +99,16 @@
9999

100100
namespace llvm {
101101

102-
extern cl::opt<bool> ForceTopDown;
103-
extern cl::opt<bool> ForceBottomUp;
102+
namespace MISched {
103+
enum Direction {
104+
Unspecified,
105+
TopDown,
106+
BottomUp,
107+
Bidirectional,
108+
};
109+
} // namespace MISched
110+
111+
extern cl::opt<MISched::Direction> PreRADirection;
104112
extern cl::opt<bool> VerifyScheduling;
105113
#ifndef NDEBUG
106114
extern cl::opt<bool> ViewMISchedDAGs;

‎llvm/lib/CodeGen/MachineScheduler.cpp‎

Lines changed: 39 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -77,30 +77,30 @@ STATISTIC(NumClustered, "Number of load/store pairs clustered");
7777

7878
namespace llvm {
7979

80-
cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
81-
cl::desc("Force top-down list scheduling"));
82-
cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
83-
cl::desc("Force bottom-up list scheduling"));
84-
namespace MISchedPostRASched {
85-
enum Direction {
86-
TopDown,
87-
BottomUp,
88-
Bidirectional,
89-
};
90-
} // end namespace MISchedPostRASched
91-
cl::opt<MISchedPostRASched::Direction> PostRADirection(
80+
cl::opt<MISched::Direction> PreRADirection(
81+
"misched-prera-direction", cl::Hidden,
82+
cl::desc("Pre reg-alloc list scheduling direction"),
83+
cl::init(MISched::Unspecified),
84+
cl::values(
85+
clEnumValN(MISched::TopDown, "topdown",
86+
"Force top-down pre reg-alloc list scheduling"),
87+
clEnumValN(MISched::BottomUp, "bottomup",
88+
"Force bottom-up pre reg-alloc list scheduling"),
89+
clEnumValN(MISched::Bidirectional, "bidirectional",
90+
"Force bidirectional pre reg-alloc list scheduling")));
91+
92+
cl::opt<MISched::Direction> PostRADirection(
9293
"misched-postra-direction", cl::Hidden,
9394
cl::desc("Post reg-alloc list scheduling direction"),
94-
// Default to top-down because it was implemented first and existing targets
95-
// expect that behavior by default.
96-
cl::init(MISchedPostRASched::TopDown),
95+
cl::init(MISched::Unspecified),
9796
cl::values(
98-
clEnumValN(MISchedPostRASched::TopDown, "topdown",
97+
clEnumValN(MISched::TopDown, "topdown",
9998
"Force top-down post reg-alloc list scheduling"),
100-
clEnumValN(MISchedPostRASched::BottomUp, "bottomup",
99+
clEnumValN(MISched::BottomUp, "bottomup",
101100
"Force bottom-up post reg-alloc list scheduling"),
102-
clEnumValN(MISchedPostRASched::Bidirectional, "bidirectional",
101+
clEnumValN(MISched::Bidirectional, "bidirectional",
103102
"Force bidirectional post reg-alloc list scheduling")));
103+
104104
cl::opt<bool>
105105
DumpCriticalPathLength("misched-dcpl", cl::Hidden,
106106
cl::desc("Print critical path length to stdout"));
@@ -3307,19 +3307,15 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
33073307
RegionPolicy.ShouldTrackLaneMasks = false;
33083308
}
33093309

3310-
// Check -misched-topdown/bottomup can force or unforce scheduling direction.
3311-
// e.g. -misched-bottomup=false allows scheduling in both directions.
3312-
assert((!ForceTopDown || !ForceBottomUp) &&
3313-
"-misched-topdown incompatible with -misched-bottomup");
3314-
if (ForceBottomUp.getNumOccurrences() > 0) {
3315-
RegionPolicy.OnlyBottomUp = ForceBottomUp;
3316-
if (RegionPolicy.OnlyBottomUp)
3317-
RegionPolicy.OnlyTopDown = false;
3318-
}
3319-
if (ForceTopDown.getNumOccurrences() > 0) {
3320-
RegionPolicy.OnlyTopDown = ForceTopDown;
3321-
if (RegionPolicy.OnlyTopDown)
3322-
RegionPolicy.OnlyBottomUp = false;
3310+
if (PreRADirection == MISched::TopDown) {
3311+
RegionPolicy.OnlyTopDown = true;
3312+
RegionPolicy.OnlyBottomUp = false;
3313+
} else if (PreRADirection == MISched::BottomUp) {
3314+
RegionPolicy.OnlyTopDown = false;
3315+
RegionPolicy.OnlyBottomUp = true;
3316+
} else if (PreRADirection == MISched::Bidirectional) {
3317+
RegionPolicy.OnlyBottomUp = false;
3318+
RegionPolicy.OnlyTopDown = false;
33233319
}
33243320
}
33253321

@@ -3911,17 +3907,15 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
39113907
MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, NumRegionInstrs);
39123908

39133909
// After subtarget overrides, apply command line options.
3914-
if (PostRADirection.getNumOccurrences() > 0) {
3915-
if (PostRADirection == MISchedPostRASched::TopDown) {
3916-
RegionPolicy.OnlyTopDown = true;
3917-
RegionPolicy.OnlyBottomUp = false;
3918-
} else if (PostRADirection == MISchedPostRASched::BottomUp) {
3919-
RegionPolicy.OnlyTopDown = false;
3920-
RegionPolicy.OnlyBottomUp = true;
3921-
} else if (PostRADirection == MISchedPostRASched::Bidirectional) {
3922-
RegionPolicy.OnlyBottomUp = false;
3923-
RegionPolicy.OnlyTopDown = false;
3924-
}
3910+
if (PostRADirection == MISched::TopDown) {
3911+
RegionPolicy.OnlyTopDown = true;
3912+
RegionPolicy.OnlyBottomUp = false;
3913+
} else if (PostRADirection == MISched::BottomUp) {
3914+
RegionPolicy.OnlyTopDown = false;
3915+
RegionPolicy.OnlyBottomUp = true;
3916+
} else if (PostRADirection == MISched::Bidirectional) {
3917+
RegionPolicy.OnlyBottomUp = false;
3918+
RegionPolicy.OnlyTopDown = false;
39253919
}
39263920
}
39273921

@@ -4368,10 +4362,9 @@ class InstructionShuffler : public MachineSchedStrategy {
43684362
} // end anonymous namespace
43694363

43704364
static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
4371-
bool Alternate = !ForceTopDown && !ForceBottomUp;
4372-
bool TopDown = !ForceBottomUp;
4373-
assert((TopDown || !ForceTopDown) &&
4374-
"-misched-topdown incompatible with -misched-bottomup");
4365+
bool Alternate =
4366+
PreRADirection != MISched::TopDown && PreRADirection != MISched::BottomUp;
4367+
bool TopDown = PreRADirection != MISched::BottomUp;
43754368
return new ScheduleDAGMILive(
43764369
C, std::make_unique<InstructionShuffler>(Alternate, TopDown));
43774370
}

‎llvm/lib/CodeGen/VLIWMachineScheduler.cpp‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -297,9 +297,6 @@ void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) {
297297
HighPressureSets[i] =
298298
((float)MaxPressure[i] > ((float)Limit * RPThreshold));
299299
}
300-
301-
assert((!ForceTopDown || !ForceBottomUp) &&
302-
"-misched-topdown incompatible with -misched-bottomup");
303300
}
304301

305302
VLIWResourceModel *ConvergingVLIWScheduler::createVLIWResourceModel(
@@ -954,7 +951,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
954951
return nullptr;
955952
}
956953
SUnit *SU;
957-
if (ForceTopDown) {
954+
if (PreRADirection == MISched::TopDown) {
958955
SU = Top.pickOnlyChoice();
959956
if (!SU) {
960957
SchedCandidate TopCand;
@@ -965,7 +962,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
965962
SU = TopCand.SU;
966963
}
967964
IsTopNode = true;
968-
} else if (ForceBottomUp) {
965+
} else if (PreRADirection == MISched::BottomUp) {
969966
SU = Bot.pickOnlyChoice();
970967
if (!SU) {
971968
SchedCandidate BotCand;

‎llvm/test/CodeGen/AArch64/dump-schedule-trace.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
22
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
3-
# RUN: -misched-topdown=true -sched-print-cycles=true \
3+
# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
44
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
55
# RUN: 2>&1 | FileCheck %s --check-prefix=TOP --strict-whitespace
66

77
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
88
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
9-
# RUN: -misched-bottomup=true -sched-print-cycles=true \
9+
# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
1010
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
1111
# RUN: 2>&1 | FileCheck %s --check-prefix=BOTTOM --strict-whitespace
1212

‎llvm/test/CodeGen/AArch64/force-enable-intervals.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
22
# RUN: -misched-dump-reserved-cycles=true \
33
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
4-
# RUN: -o - %s 2>&1 -misched-topdown| FileCheck %s
4+
# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
55

66
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
77
# RUN: -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \
88
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
9-
# RUN: -o - %s 2>&1 -misched-topdown| FileCheck %s --check-prefix=FORCE
9+
# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s --check-prefix=FORCE
1010

1111
# REQUIRES: asserts, aarch64-registered-target
1212
---

‎llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -mcpu=cortex-a55 %s -o - 2>&1 \
22
# RUN: -misched-dump-reserved-cycles=true \
33
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
4-
# RUN: -misched-bottomup=true -sched-print-cycles=true \
4+
# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
55
# RUN: -misched-detail-resource-booking=true \
66
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
77
# RUN: | FileCheck %s

‎llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
22
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
3-
# RUN: -misched-bottomup=true -sched-print-cycles=true \
3+
# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
44
# RUN: -misched-dump-reserved-cycles=true -misched-detail-resource-booking=true\
55
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
66
# RUN: 2>&1 | FileCheck %s

‎llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \
22
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
3-
# RUN: -misched-topdown=true -sched-print-cycles=true \
3+
# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
44
# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=true 2>&1 | FileCheck --check-prefix=SORTED %s
55

66
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \
77
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
8-
# RUN: -misched-topdown=true -sched-print-cycles=true \
8+
# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
99
# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s
1010

1111
# REQUIRES: asserts, aarch64-registered-target

‎llvm/test/CodeGen/ARM/single-issue-r52.mir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
2-
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
3-
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
4-
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
1+
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
2+
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
3+
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
4+
# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
55
# REQUIRES: asserts
66
--- |
77
; ModuleID = 'foo.ll'

‎llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=machine-scheduler \
22
# RUN: -debug-only=machine-scheduler -misched-dump-schedule-trace \
3-
# RUN: -misched-topdown -o - %s 2>&1 | FileCheck %s
3+
# RUN: -misched-prera-direction=topdown -o - %s 2>&1 | FileCheck %s
44
# REQUIRES: asserts
55

66
# The purpose of this test is to show that the VADD instructions are issued so

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