[AArch64][NFC] Add test for vector udiv scalarization

Author: SavchenkoValeriy

llvm/test/CodeGen/AArch64/udiv-by-const-promoted-ops.ll

@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
+
+; This test verifies that udiv by constant works correctly even when type
+; legalization promotes constant operands (e.g., i16 -> i32 in BUILD_VECTOR).
+; This is a regression test for a bug where v16i16 would be split into two
+; v8i16 operations during legalization, the i16 constants would be promoted
+; to i32, and then the second DAGCombine round would fail to recognize the
+; promoted constants when trying to convert udiv into mul+shift.
+
+define <8 x i16> @udiv_v8i16_by_255(<8 x i16> %x) {
+; CHECK-LABEL: udiv_v8i16_by_255:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #32897 // =0x8081
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    umull2 v2.4s, v0.8h, v1.8h
+; CHECK-NEXT:    umull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v2.8h
+; CHECK-NEXT:    ushr v0.8h, v0.8h, #7
+; CHECK-NEXT:    ret
+  %div = udiv <8 x i16> %x, splat (i16 255)
+  ret <8 x i16> %div
+}
+
+define <16 x i16> @udiv_v16i16_by_255(<16 x i16> %x) {
+; CHECK-LABEL: udiv_v16i16_by_255:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w9, v0.h[0]
+; CHECK-NEXT:    umov w11, v1.h[0]
+; CHECK-NEXT:    mov w8, #258 // =0x102
+; CHECK-NEXT:    movk w8, #257, lsl #16
+; CHECK-NEXT:    umov w10, v0.h[1]
+; CHECK-NEXT:    umov w12, v1.h[1]
+; CHECK-NEXT:    umov w13, v0.h[2]
+; CHECK-NEXT:    umov w14, v1.h[2]
+; CHECK-NEXT:    umull x9, w9, w8
+; CHECK-NEXT:    umull x11, w11, w8
+; CHECK-NEXT:    umull x10, w10, w8
+; CHECK-NEXT:    umull x12, w12, w8
+; CHECK-NEXT:    lsr x9, x9, #32
+; CHECK-NEXT:    lsr x11, x11, #32
+; CHECK-NEXT:    umull x13, w13, w8
+; CHECK-NEXT:    fmov s2, w9
+; CHECK-NEXT:    lsr x10, x10, #32
+; CHECK-NEXT:    umov w9, v0.h[3]
+; CHECK-NEXT:    fmov s3, w11
+; CHECK-NEXT:    lsr x12, x12, #32
+; CHECK-NEXT:    umull x11, w14, w8
+; CHECK-NEXT:    umov w14, v1.h[3]
+; CHECK-NEXT:    mov v2.h[1], w10
+; CHECK-NEXT:    lsr x10, x13, #32
+; CHECK-NEXT:    mov v3.h[1], w12
+; CHECK-NEXT:    umov w12, v0.h[4]
+; CHECK-NEXT:    lsr x11, x11, #32
+; CHECK-NEXT:    umull x9, w9, w8
+; CHECK-NEXT:    umull x13, w14, w8
+; CHECK-NEXT:    umov w14, v1.h[4]
+; CHECK-NEXT:    mov v2.h[2], w10
+; CHECK-NEXT:    mov v3.h[2], w11
+; CHECK-NEXT:    lsr x9, x9, #32
+; CHECK-NEXT:    umull x10, w12, w8
+; CHECK-NEXT:    lsr x12, x13, #32
+; CHECK-NEXT:    umov w11, v0.h[5]
+; CHECK-NEXT:    umull x13, w14, w8
+; CHECK-NEXT:    umov w14, v1.h[5]
+; CHECK-NEXT:    mov v2.h[3], w9
+; CHECK-NEXT:    lsr x9, x10, #32
+; CHECK-NEXT:    mov v3.h[3], w12
+; CHECK-NEXT:    lsr x12, x13, #32
+; CHECK-NEXT:    umull x10, w11, w8
+; CHECK-NEXT:    umov w11, v0.h[6]
+; CHECK-NEXT:    umull x13, w14, w8
+; CHECK-NEXT:    umov w14, v1.h[6]
+; CHECK-NEXT:    mov v2.h[4], w9
+; CHECK-NEXT:    umov w9, v0.h[7]
+; CHECK-NEXT:    mov v3.h[4], w12
+; CHECK-NEXT:    lsr x10, x10, #32
+; CHECK-NEXT:    lsr x12, x13, #32
+; CHECK-NEXT:    umull x11, w11, w8
+; CHECK-NEXT:    umull x13, w14, w8
+; CHECK-NEXT:    umov w14, v1.h[7]
+; CHECK-NEXT:    mov v2.h[5], w10
+; CHECK-NEXT:    umull x9, w9, w8
+; CHECK-NEXT:    mov v3.h[5], w12
+; CHECK-NEXT:    lsr x10, x11, #32
+; CHECK-NEXT:    lsr x11, x13, #32
+; CHECK-NEXT:    umull x8, w14, w8
+; CHECK-NEXT:    lsr x9, x9, #32
+; CHECK-NEXT:    mov v2.h[6], w10
+; CHECK-NEXT:    mov v3.h[6], w11
+; CHECK-NEXT:    lsr x8, x8, #32
+; CHECK-NEXT:    mov v2.h[7], w9
+; CHECK-NEXT:    mov v3.h[7], w8
+; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    mov v1.16b, v3.16b
+; CHECK-NEXT:    ret
+  %div = udiv <16 x i16> %x, splat (i16 255)
+  ret <16 x i16> %div
+}