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ShoreshenShoreshen
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fix comments
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2 files changed

+50
-52
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

Lines changed: 48 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -4292,14 +4292,15 @@ enum srcStatus {
42924292
LAST_STAT = IS_LOWER_HALF_NEG
42934293
};
42944294

4295-
bool isTruncHalf(MachineInstr *MI, const MachineRegisterInfo &MRI) {
4295+
static bool isTruncHalf(const MachineInstr *MI,
4296+
const MachineRegisterInfo &MRI) {
42964297
assert(MI->getOpcode() == AMDGPU::G_TRUNC);
42974298
unsigned dstSize = MRI.getType(MI->getOperand(0).getReg()).getSizeInBits();
42984299
unsigned srcSize = MRI.getType(MI->getOperand(1).getReg()).getSizeInBits();
42994300
return dstSize * 2 == srcSize;
43004301
}
43014302

4302-
bool isLshrHalf(MachineInstr *MI, const MachineRegisterInfo &MRI) {
4303+
static bool isLshrHalf(const MachineInstr *MI, const MachineRegisterInfo &MRI) {
43034304
assert(MI->getOpcode() == AMDGPU::G_LSHR);
43044305
Register ShiftSrc;
43054306
std::optional<ValueAndVReg> ShiftAmt;
@@ -4312,7 +4313,7 @@ bool isLshrHalf(MachineInstr *MI, const MachineRegisterInfo &MRI) {
43124313
return false;
43134314
}
43144315

4315-
bool isShlHalf(MachineInstr *MI, const MachineRegisterInfo &MRI) {
4316+
static bool isShlHalf(const MachineInstr *MI, const MachineRegisterInfo &MRI) {
43164317
assert(MI->getOpcode() == AMDGPU::G_SHL);
43174318
Register ShiftSrc;
43184319
std::optional<ValueAndVReg> ShiftAmt;
@@ -4325,8 +4326,8 @@ bool isShlHalf(MachineInstr *MI, const MachineRegisterInfo &MRI) {
43254326
return false;
43264327
}
43274328

4328-
bool retOpStat(MachineOperand *Op, int stat,
4329-
std::pair<MachineOperand *, int> &curr) {
4329+
static bool retOpStat(const MachineOperand *Op, int stat,
4330+
std::pair<const MachineOperand *, int> &curr) {
43304331
if ((Op->isReg() && !(Op->getReg().isPhysical())) || Op->isImm() ||
43314332
Op->isCImm() || Op->isFPImm()) {
43324333
curr = {Op, stat};
@@ -4335,15 +4336,14 @@ bool retOpStat(MachineOperand *Op, int stat,
43354336
return false;
43364337
}
43374338

4338-
bool calcNextStatus(std::pair<MachineOperand *, int> &curr,
4339-
const MachineRegisterInfo &MRI) {
4339+
static bool calcNextStatus(std::pair<const MachineOperand *, int> &curr,
4340+
const MachineRegisterInfo &MRI) {
43404341
if (!curr.first->isReg()) {
43414342
return false;
43424343
}
4343-
MachineInstr *MI = nullptr;
4344+
const MachineInstr *MI = nullptr;
43444345

43454346
if (!curr.first->isDef()) {
4346-
// MRI.getVRegDef falls into infinite loop if use define reg
43474347
MI = MRI.getVRegDef(curr.first->getReg());
43484348
} else {
43494349
MI = curr.first->getParent();
@@ -4434,12 +4434,12 @@ bool calcNextStatus(std::pair<MachineOperand *, int> &curr,
44344434
return false;
44354435
}
44364436

4437-
std::vector<std::pair<MachineOperand *, int>>
4438-
getSrcStats(MachineOperand *Op, const MachineRegisterInfo &MRI,
4437+
SmallVector<std::pair<const MachineOperand *, int>>
4438+
getSrcStats(const MachineOperand *Op, const MachineRegisterInfo &MRI,
44394439
bool onlyLastSameOrNeg = false, int maxDepth = 6) {
44404440
int depth = 0;
4441-
std::pair<MachineOperand *, int> curr = {Op, IS_SAME};
4442-
std::vector<std::pair<MachineOperand *, int>> statList;
4441+
std::pair<const MachineOperand *, int> curr = {Op, IS_SAME};
4442+
SmallVector<std::pair<const MachineOperand *, int>> statList;
44434443

44444444
while (true) {
44454445
depth++;
@@ -4460,27 +4460,23 @@ getSrcStats(MachineOperand *Op, const MachineRegisterInfo &MRI,
44604460
return statList;
44614461
}
44624462

4463-
bool isInlinableConstant(MachineOperand *Op, const SIInstrInfo &TII) {
4464-
bool a = TII.isInlineConstant(*Op);
4465-
switch (Op->getType()) {
4466-
case MachineOperand::MachineOperandType::MO_Immediate:
4467-
return TII.isInlineConstant(*Op);
4468-
case MachineOperand::MachineOperandType::MO_CImmediate:
4469-
return TII.isInlineConstant(Op->getCImm()->getValue());
4470-
case MachineOperand::MachineOperandType::MO_FPImmediate:
4471-
return TII.isInlineConstant(Op->getFPImm()->getValueAPF());
4463+
static bool isInlinableConstant(const MachineOperand &Op,
4464+
const SIInstrInfo &TII) {
4465+
if (Op.isFPImm()) {
4466+
return TII.isInlineConstant(Op.getFPImm()->getValueAPF());
44724467
}
44734468
return false;
44744469
}
44754470

4476-
bool isSameBitWidth(MachineOperand *Op1, MachineOperand *Op2,
4477-
const MachineRegisterInfo &MRI) {
4471+
static bool isSameBitWidth(const MachineOperand *Op1, const MachineOperand *Op2,
4472+
const MachineRegisterInfo &MRI) {
44784473
unsigned width1 = MRI.getType(Op1->getReg()).getSizeInBits();
44794474
unsigned width2 = MRI.getType(Op2->getReg()).getSizeInBits();
44804475
return width1 == width2;
44814476
}
44824477

4483-
bool isSameOperand(MachineOperand *Op1, MachineOperand *Op2) {
4478+
static bool isSameOperand(const MachineOperand *Op1,
4479+
const MachineOperand *Op2) {
44844480
if (Op1->isReg()) {
44854481
if (Op2->isReg()) {
44864482
return Op1->getReg() == Op2->getReg();
@@ -4490,9 +4486,10 @@ bool isSameOperand(MachineOperand *Op1, MachineOperand *Op2) {
44904486
return Op1->isIdenticalTo(*Op2);
44914487
}
44924488

4493-
bool validToPack(int HiStat, int LoStat, unsigned int &Mods,
4494-
MachineOperand *newOp, MachineOperand *RootOp,
4495-
const SIInstrInfo &TII, const MachineRegisterInfo &MRI) {
4489+
static bool validToPack(int HiStat, int LoStat, unsigned int &Mods,
4490+
const MachineOperand *newOp,
4491+
const MachineOperand *RootOp, const SIInstrInfo &TII,
4492+
const MachineRegisterInfo &MRI) {
44964493
if (newOp->isReg()) {
44974494
if (isSameBitWidth(newOp, RootOp, MRI)) {
44984495
// IS_LOWER_HALF remain 0
@@ -4517,7 +4514,7 @@ bool validToPack(int HiStat, int LoStat, unsigned int &Mods,
45174514
} else {
45184515
if ((HiStat == IS_SAME || HiStat == IS_NEG) &&
45194516
(LoStat == IS_SAME || LoStat == IS_NEG) &&
4520-
isInlinableConstant(newOp, TII)) {
4517+
isInlinableConstant(*newOp, TII)) {
45214518
if (HiStat == IS_NEG) {
45224519
Mods ^= SISrcMods::NEG_HI;
45234520
}
@@ -4532,13 +4529,13 @@ bool validToPack(int HiStat, int LoStat, unsigned int &Mods,
45324529
return false;
45334530
}
45344531

4535-
std::pair<MachineOperand *, unsigned>
4536-
AMDGPUInstructionSelector::selectVOP3PModsImpl(MachineOperand *Op,
4532+
std::pair<const MachineOperand *, unsigned>
4533+
AMDGPUInstructionSelector::selectVOP3PModsImpl(const MachineOperand *Op,
45374534
const MachineRegisterInfo &MRI,
45384535
bool IsDOT) const {
45394536
unsigned Mods = 0;
4540-
MachineOperand *RootOp = Op;
4541-
std::pair<MachineOperand *, int> stat = getSrcStats(Op, MRI, true)[0];
4537+
const MachineOperand *RootOp = Op;
4538+
std::pair<const MachineOperand *, int> stat = getSrcStats(Op, MRI, true)[0];
45424539
if (!stat.first->isReg()) {
45434540
Mods |= SISrcMods::OP_SEL_1;
45444541
return {Op, Mods};
@@ -4550,8 +4547,8 @@ AMDGPUInstructionSelector::selectVOP3PModsImpl(MachineOperand *Op,
45504547
MachineInstr *MI = MRI.getVRegDef(Op->getReg());
45514548
if (MI->getOpcode() == AMDGPU::G_BUILD_VECTOR && MI->getNumOperands() == 3 &&
45524549
(!IsDOT || !Subtarget->hasDOTOpSelHazard())) {
4553-
std::vector<std::pair<MachineOperand *, int>> statList_Hi;
4554-
std::vector<std::pair<MachineOperand *, int>> statList_Lo;
4550+
SmallVector<std::pair<const MachineOperand *, int>> statList_Hi;
4551+
SmallVector<std::pair<const MachineOperand *, int>> statList_Lo;
45554552
statList_Hi = getSrcStats(&MI->getOperand(2), MRI);
45564553
if (statList_Hi.size() != 0) {
45574554
statList_Lo = getSrcStats(&MI->getOperand(1), MRI);
@@ -4575,30 +4572,29 @@ AMDGPUInstructionSelector::selectVOP3PModsImpl(MachineOperand *Op,
45754572
return {Op, Mods};
45764573
}
45774574

4578-
int64_t getAllKindImm(MachineOperand *Op) {
4575+
int64_t getAllKindImm(const MachineOperand *Op) {
45794576
switch (Op->getType()) {
45804577
case MachineOperand::MachineOperandType::MO_Immediate:
45814578
return Op->getImm();
45824579
case MachineOperand::MachineOperandType::MO_CImmediate:
45834580
return Op->getCImm()->getSExtValue();
4584-
break;
45854581
case MachineOperand::MachineOperandType::MO_FPImmediate:
45864582
return Op->getFPImm()->getValueAPF().bitcastToAPInt().getSExtValue();
4587-
break;
45884583
}
45894584
llvm_unreachable("not an imm type");
45904585
}
45914586

4592-
bool checkRB(MachineOperand *Op, int RBNo, const AMDGPURegisterBankInfo &RBI,
4593-
const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) {
4587+
bool checkRB(const MachineOperand *Op, int RBNo,
4588+
const AMDGPURegisterBankInfo &RBI, const MachineRegisterInfo &MRI,
4589+
const TargetRegisterInfo &TRI) {
45944590
const RegisterBank *RB = RBI.getRegBank(Op->getReg(), MRI, TRI);
45954591
return RB->getID() == RBNo;
45964592
}
45974593

4598-
MachineOperand *getVReg(MachineOperand *newOp, MachineOperand *RootOp,
4599-
const AMDGPURegisterBankInfo &RBI,
4600-
MachineRegisterInfo &MRI,
4601-
const TargetRegisterInfo &TRI) {
4594+
const MachineOperand *
4595+
getVReg(const MachineOperand *newOp, const MachineOperand *RootOp,
4596+
const AMDGPURegisterBankInfo &RBI, MachineRegisterInfo &MRI,
4597+
const TargetRegisterInfo &TRI, const SIInstrInfo &TII) {
46024598
// RootOp can only be VGPR or SGPR (some hand written cases such as
46034599
// inst-select-ashr.v2s16.mir::ashr_v2s16_vs)
46044600
if (checkRB(RootOp, AMDGPU::SGPRRegBankID, RBI, MRI, TRI) ||
@@ -4612,13 +4608,14 @@ MachineOperand *getVReg(MachineOperand *newOp, MachineOperand *RootOp,
46124608
return RootOp;
46134609
}
46144610

4611+
MachineBasicBlock *BB = MI->getParent();
46154612
const TargetRegisterClass *DstRC =
46164613
TRI.getConstrainedRegClassForOperand(*RootOp, MRI);
46174614
Register dstReg = MRI.createVirtualRegister(DstRC);
46184615

4619-
MachineIRBuilder B(*RootOp->getParent());
46204616
MachineInstrBuilder MIB =
4621-
B.buildInstr(AMDGPU::COPY).addDef(dstReg).addUse(newOp->getReg());
4617+
BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), dstReg)
4618+
.addReg(newOp->getReg());
46224619

46234620
// only accept VGPR
46244621
return &MIB->getOperand(0);
@@ -4629,14 +4626,15 @@ AMDGPUInstructionSelector::selectVOP3PMods(MachineOperand &Root) const {
46294626
MachineRegisterInfo &MRI
46304627
= Root.getParent()->getParent()->getParent()->getRegInfo();
46314628

4632-
std::pair<MachineOperand *, unsigned> res = selectVOP3PModsImpl(&Root, MRI);
4629+
std::pair<const MachineOperand *, unsigned> res =
4630+
selectVOP3PModsImpl(&Root, MRI);
46334631
if (!(res.first->isReg())) {
46344632
return {{
46354633
[=](MachineInstrBuilder &MIB) { MIB.addImm(getAllKindImm(res.first)); },
46364634
[=](MachineInstrBuilder &MIB) { MIB.addImm(res.second); } // src_mods
46374635
}};
46384636
}
4639-
res.first = getVReg(res.first, &Root, RBI, MRI, TRI);
4637+
res.first = getVReg(res.first, &Root, RBI, MRI, TRI, TII);
46404638
return {{
46414639
[=](MachineInstrBuilder &MIB) { MIB.addReg(res.first->getReg()); },
46424640
[=](MachineInstrBuilder &MIB) { MIB.addImm(res.second); } // src_mods
@@ -4648,15 +4646,15 @@ AMDGPUInstructionSelector::selectVOP3PModsDOT(MachineOperand &Root) const {
46484646
MachineRegisterInfo &MRI
46494647
= Root.getParent()->getParent()->getParent()->getRegInfo();
46504648

4651-
std::pair<MachineOperand *, unsigned> res =
4649+
std::pair<const MachineOperand *, unsigned> res =
46524650
selectVOP3PModsImpl(&Root, MRI, true);
46534651
if (!(res.first->isReg())) {
46544652
return {{
46554653
[=](MachineInstrBuilder &MIB) { MIB.addImm(getAllKindImm(res.first)); },
46564654
[=](MachineInstrBuilder &MIB) { MIB.addImm(res.second); } // src_mods
46574655
}};
46584656
}
4659-
res.first = getVReg(res.first, &Root, RBI, MRI, TRI);
4657+
res.first = getVReg(res.first, &Root, RBI, MRI, TRI, TII);
46604658
return {{
46614659
[=](MachineInstrBuilder &MIB) { MIB.addReg(res.first->getReg()); },
46624660
[=](MachineInstrBuilder &MIB) { MIB.addImm(res.second); } // src_mods

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -187,8 +187,8 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
187187

188188
ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
189189

190-
std::pair<MachineOperand *, unsigned>
191-
selectVOP3PModsImpl(MachineOperand *Op, const MachineRegisterInfo &MRI,
190+
std::pair<const MachineOperand *, unsigned>
191+
selectVOP3PModsImpl(const MachineOperand *Op, const MachineRegisterInfo &MRI,
192192
bool IsDOT = false) const;
193193

194194
InstructionSelector::ComplexRendererFns

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