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Merge branch 'main' into minimal_runtime_args
2 parents 8d9e3cf + c1add93 commit dad23bc

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‎libc/config/gpu/amdgpu/entrypoints.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -282,6 +282,7 @@ set(TARGET_LIBM_ENTRYPOINTS
282282
# math.h entrypoints
283283
libc.src.math.acos
284284
libc.src.math.acosf
285+
libc.src.math.acoshf
285286
libc.src.math.asin
286287
libc.src.math.asinf
287288
libc.src.math.asinhf

‎libcxx/include/__exception/exception.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ class exception { // base of all library exceptions
4848
__data_._DoFree = true;
4949
}
5050

51-
exception(exception const&) _NOEXCEPT {}
51+
exception(exception const&) _NOEXCEPT : __data_() {}
5252

5353
exception& operator=(exception const&) _NOEXCEPT { return *this; }
5454

‎lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -620,7 +620,7 @@ static llvm::StringRef GetFormatNameOrEmpty(const RegisterInfo &reg_info) {
620620
case eFormatFloat128:
621621
return "float128";
622622
default:
623-
llvm_unreachable("Unkown register format")
623+
llvm_unreachable("Unknown register format");
624624
};
625625
}
626626

‎lldb/source/Target/Platform.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2234,7 +2234,8 @@ PlatformSP PlatformList::GetOrCreate(llvm::ArrayRef<ArchSpec> archs,
22342234
PlatformSP PlatformList::Create(llvm::StringRef name) {
22352235
std::lock_guard<std::recursive_mutex> guard(m_mutex);
22362236
PlatformSP platform_sp = Platform::Create(name);
2237-
m_platforms.push_back(platform_sp);
2237+
if (platform_sp)
2238+
m_platforms.push_back(platform_sp);
22382239
return platform_sp;
22392240
}
22402241

‎lldb/unittests/Platform/PlatformTest.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,3 +157,9 @@ TEST_F(PlatformTest, GetPlatformForArchitecturesCandidates) {
157157

158158
PlatformThumb::Terminate();
159159
}
160+
161+
TEST_F(PlatformTest, CreateUnknown) {
162+
SetHostPlatform(std::make_shared<PlatformIntel>());
163+
ASSERT_EQ(list.Create("unknown-platform-name"), nullptr);
164+
ASSERT_EQ(list.GetOrCreate("dummy"), nullptr);
165+
}

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -285,9 +285,7 @@ InstructionCost VPRecipeBase::computeCost(ElementCount VF,
285285

286286
bool VPRecipeBase::isPhi() const {
287287
return (getVPDefID() >= VPFirstPHISC && getVPDefID() <= VPLastPHISC) ||
288-
(isa<VPInstruction>(this) &&
289-
cast<VPInstruction>(this)->getOpcode() == Instruction::PHI) ||
290-
isa<VPIRPhi>(this);
288+
isa<VPPhi, VPIRPhi>(this);
291289
}
292290

293291
bool VPRecipeBase::isScalarCast() const {

‎llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll‎

Lines changed: 189 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -477,3 +477,192 @@ for.cond:
477477
for.end:
478478
ret i32 %sub
479479
}
480+
481+
define i64 @test_reduction_with_widen_induction_order_1(ptr %A, i64 %N) {
482+
; CHECK-LABEL: @test_reduction_with_widen_induction_order_1(
483+
; CHECK-NEXT: iter.check:
484+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], 4
485+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
486+
; CHECK: vector.main.loop.iter.check:
487+
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 4
488+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
489+
; CHECK: vector.ph:
490+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
491+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
492+
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
493+
; CHECK: vector.body:
494+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
495+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
496+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
497+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[INDEX]]
498+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP0]], align 4
499+
; CHECK-NEXT: [[TMP1]] = add <4 x i64> [[VEC_PHI]], [[WIDE_LOAD]]
500+
; CHECK-NEXT: store <4 x i64> [[VEC_IND]], ptr [[TMP0]], align 4
501+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
502+
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
503+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
504+
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
505+
; CHECK: middle.block:
506+
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP1]])
507+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
508+
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
509+
; CHECK: vec.epilog.iter.check:
510+
; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[N]], [[N_VEC]]
511+
; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 4
512+
; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]]
513+
; CHECK: vec.epilog.ph:
514+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
515+
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
516+
; CHECK-NEXT: [[N_MOD_VF2:%.*]] = urem i64 [[N]], 4
517+
; CHECK-NEXT: [[N_VEC3:%.*]] = sub i64 [[N]], [[N_MOD_VF2]]
518+
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> zeroinitializer, i64 [[BC_MERGE_RDX]], i32 0
519+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[BC_RESUME_VAL]], i64 0
520+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
521+
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3>
522+
; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
523+
; CHECK: vec.epilog.vector.body:
524+
; CHECK-NEXT: [[INDEX4:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT8:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
525+
; CHECK-NEXT: [[VEC_IND5:%.*]] = phi <4 x i64> [ [[INDUCTION]], [[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT9:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
526+
; CHECK-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i64> [ [[TMP4]], [[VEC_EPILOG_PH]] ], [ [[TMP6:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
527+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX4]]
528+
; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i64>, ptr [[TMP5]], align 4
529+
; CHECK-NEXT: [[TMP6]] = add <4 x i64> [[VEC_PHI6]], [[WIDE_LOAD7]]
530+
; CHECK-NEXT: store <4 x i64> [[VEC_IND5]], ptr [[TMP5]], align 4
531+
; CHECK-NEXT: [[INDEX_NEXT8]] = add nuw i64 [[INDEX4]], 4
532+
; CHECK-NEXT: [[VEC_IND_NEXT9]] = add <4 x i64> [[VEC_IND5]], splat (i64 4)
533+
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT8]], [[N_VEC3]]
534+
; CHECK-NEXT: br i1 [[TMP7]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
535+
; CHECK: vec.epilog.middle.block:
536+
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP6]])
537+
; CHECK-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC3]]
538+
; CHECK-NEXT: br i1 [[CMP_N10]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]
539+
; CHECK: vec.epilog.scalar.ph:
540+
; CHECK-NEXT: [[BC_RESUME_VAL11:%.*]] = phi i64 [ [[N_VEC3]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]
541+
; CHECK-NEXT: [[BC_MERGE_RDX12:%.*]] = phi i64 [ [[TMP8]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK]] ]
542+
; CHECK-NEXT: br label [[LOOP:%.*]]
543+
; CHECK: loop:
544+
; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL11]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ]
545+
; CHECK-NEXT: [[RED:%.*]] = phi i64 [ [[BC_MERGE_RDX12]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
546+
; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_1]]
547+
; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP_A]], align 4
548+
; CHECK-NEXT: [[RED_NEXT]] = add i64 [[RED]], [[L]]
549+
; CHECK-NEXT: store i64 [[IV_1]], ptr [[GEP_A]], align 4
550+
; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i64 [[IV_1]], 1
551+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_1_NEXT]], [[N]]
552+
; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP19:![0-9]+]]
553+
; CHECK: exit:
554+
; CHECK-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i64 [ [[RED_NEXT]], [[LOOP]] ], [ [[TMP3]], [[MIDDLE_BLOCK]] ], [ [[TMP8]], [[VEC_EPILOG_MIDDLE_BLOCK]] ]
555+
; CHECK-NEXT: ret i64 [[RED_NEXT_LCSSA]]
556+
;
557+
entry:
558+
br label %loop
559+
560+
loop:
561+
%iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]
562+
%red = phi i64 [ 0, %entry ], [ %red.next, %loop ]
563+
%gep.A = getelementptr inbounds i64, ptr %A, i64 %iv.1
564+
%l = load i64, ptr %gep.A
565+
%red.next = add i64 %red, %l
566+
store i64 %iv.1, ptr %gep.A, align 4
567+
%iv.1.next = add nuw nsw i64 %iv.1, 1
568+
%exitcond = icmp eq i64 %iv.1.next, %N
569+
br i1 %exitcond, label %exit, label %loop
570+
571+
exit:
572+
ret i64 %red.next
573+
}
574+
575+
; Same as @test_reduction_with_widen_induction_order_1, but with phi order flipped.
576+
define i64 @test_reduction_with_widen_induction_order_2(ptr %A, i64 %N) {
577+
; CHECK-LABEL: @test_reduction_with_widen_induction_order_2(
578+
; CHECK-NEXT: iter.check:
579+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], 4
580+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
581+
; CHECK: vector.main.loop.iter.check:
582+
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], 4
583+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
584+
; CHECK: vector.ph:
585+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
586+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
587+
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
588+
; CHECK: vector.body:
589+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
590+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP1:%.*]], [[VECTOR_BODY]] ]
591+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
592+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[INDEX]]
593+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP0]], align 4
594+
; CHECK-NEXT: [[TMP1]] = add <4 x i64> [[VEC_PHI]], [[WIDE_LOAD]]
595+
; CHECK-NEXT: store <4 x i64> [[VEC_IND]], ptr [[TMP0]], align 4
596+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
597+
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
598+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
599+
; CHECK-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
600+
; CHECK: middle.block:
601+
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP1]])
602+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
603+
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
604+
; CHECK: vec.epilog.iter.check:
605+
; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[N]], [[N_VEC]]
606+
; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 4
607+
; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]]
608+
; CHECK: vec.epilog.ph:
609+
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
610+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
611+
; CHECK-NEXT: [[N_MOD_VF2:%.*]] = urem i64 [[N]], 4
612+
; CHECK-NEXT: [[N_VEC3:%.*]] = sub i64 [[N]], [[N_MOD_VF2]]
613+
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> zeroinitializer, i64 [[BC_MERGE_RDX]], i32 0
614+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[BC_RESUME_VAL]], i64 0
615+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
616+
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3>
617+
; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
618+
; CHECK: vec.epilog.vector.body:
619+
; CHECK-NEXT: [[INDEX4:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT8:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
620+
; CHECK-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i64> [ [[TMP4]], [[VEC_EPILOG_PH]] ], [ [[TMP6:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
621+
; CHECK-NEXT: [[VEC_IND6:%.*]] = phi <4 x i64> [ [[INDUCTION]], [[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT9:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
622+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX4]]
623+
; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i64>, ptr [[TMP5]], align 4
624+
; CHECK-NEXT: [[TMP6]] = add <4 x i64> [[VEC_PHI5]], [[WIDE_LOAD7]]
625+
; CHECK-NEXT: store <4 x i64> [[VEC_IND6]], ptr [[TMP5]], align 4
626+
; CHECK-NEXT: [[INDEX_NEXT8]] = add nuw i64 [[INDEX4]], 4
627+
; CHECK-NEXT: [[VEC_IND_NEXT9]] = add <4 x i64> [[VEC_IND6]], splat (i64 4)
628+
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT8]], [[N_VEC3]]
629+
; CHECK-NEXT: br i1 [[TMP7]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
630+
; CHECK: vec.epilog.middle.block:
631+
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP6]])
632+
; CHECK-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[N]], [[N_VEC3]]
633+
; CHECK-NEXT: br i1 [[CMP_N10]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]
634+
; CHECK: vec.epilog.scalar.ph:
635+
; CHECK-NEXT: [[BC_MERGE_RDX11:%.*]] = phi i64 [ [[TMP8]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]
636+
; CHECK-NEXT: [[BC_RESUME_VAL12:%.*]] = phi i64 [ [[N_VEC3]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK]] ]
637+
; CHECK-NEXT: br label [[LOOP:%.*]]
638+
; CHECK: loop:
639+
; CHECK-NEXT: [[RED:%.*]] = phi i64 [ [[BC_MERGE_RDX11]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
640+
; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL12]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ]
641+
; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_1]]
642+
; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP_A]], align 4
643+
; CHECK-NEXT: [[RED_NEXT]] = add i64 [[RED]], [[L]]
644+
; CHECK-NEXT: store i64 [[IV_1]], ptr [[GEP_A]], align 4
645+
; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i64 [[IV_1]], 1
646+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_1_NEXT]], [[N]]
647+
; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP22:![0-9]+]]
648+
; CHECK: exit:
649+
; CHECK-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i64 [ [[RED_NEXT]], [[LOOP]] ], [ [[TMP3]], [[MIDDLE_BLOCK]] ], [ [[TMP8]], [[VEC_EPILOG_MIDDLE_BLOCK]] ]
650+
; CHECK-NEXT: ret i64 [[RED_NEXT_LCSSA]]
651+
;
652+
entry:
653+
br label %loop
654+
655+
loop:
656+
%red = phi i64 [ 0, %entry ], [ %red.next, %loop ]
657+
%iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]
658+
%gep.A = getelementptr inbounds i64, ptr %A, i64 %iv.1
659+
%l = load i64, ptr %gep.A
660+
%red.next = add i64 %red, %l
661+
store i64 %iv.1, ptr %gep.A, align 4
662+
%iv.1.next = add nuw nsw i64 %iv.1, 1
663+
%exitcond = icmp eq i64 %iv.1.next, %N
664+
br i1 %exitcond, label %exit, label %loop
665+
666+
exit:
667+
ret i64 %red.next
668+
}

‎llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ unittest("LLVMFrontendTests") {
1515
sources = [
1616
"HLSLBindingTest.cpp",
1717
"HLSLRootSignatureDumpTest.cpp",
18-
"HLSLRootSignatureRangesTest.cpp",
1918
"OpenACCTest.cpp",
2019
"OpenMPCompositionTest.cpp",
2120
"OpenMPContextTest.cpp",

‎mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -451,7 +451,7 @@ def SPIRV_GlobalVariableOp : SPIRV_Op<"GlobalVariable", [InModuleScope, Symbol]>
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OptionalAttr<I32Attr>:$location,
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OptionalAttr<I32Attr>:$binding,
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OptionalAttr<I32Attr>:$descriptor_set,
454-
OptionalAttr<StrAttr>:$builtin,
454+
OptionalAttr<StrAttr>:$built_in,
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OptionalAttr<SPIRV_LinkageAttributesAttr>:$linkage_attributes
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);
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‎offload/unittests/CMakeLists.txt‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@ if (NOT TARGET llvm_gtest)
1515
return ()
1616
endif ()
1717

18+
set(OFFLOAD_UNITTESTS_DIR ${CMAKE_CURRENT_SOURCE_DIR})
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function(add_offload_test_device_code test_filename test_name)
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set(SRC_PATH ${CMAKE_CURRENT_SOURCE_DIR}/${test_filename})
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set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
@@ -39,6 +41,7 @@ function(add_offload_test_device_code test_filename test_name)
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add_custom_command(
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OUTPUT ${output_file}
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COMMAND ${CMAKE_CXX_COMPILER}
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-I${OFFLOAD_UNITTESTS_DIR}
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--target=nvptx64-nvidia-cuda -march=${nvptx_arch}
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-nogpulib --cuda-path=${cuda_path} -flto ${ARGN}
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${SRC_PATH} -o ${output_file}
@@ -63,6 +66,7 @@ function(add_offload_test_device_code test_filename test_name)
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add_custom_command(
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OUTPUT ${output_file}
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COMMAND ${CMAKE_CXX_COMPILER}
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-I${OFFLOAD_UNITTESTS_DIR}
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--target=amdgcn-amd-amdhsa -mcpu=${amdgpu_arch}
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-nogpulib -flto ${ARGN} ${SRC_PATH} -o ${output_file}
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DEPENDS ${SRC_PATH}

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