Skip to content

Commit daff757

Browse files
topperctopperc
committed
Pre-commit tests
1 parent 3720d8b commit daff757

File tree

5 files changed

+134
-0
lines changed

5 files changed

+134
-0
lines changed

‎llvm/test/CodeGen/RISCV/rv32xandesperf.ll‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -364,6 +364,20 @@ define i32 @sexti1_i32_2(i1 %a) {
364364
ret i32 %1
365365
}
366366

367+
; Make sure we don't use not+nds.bfos
368+
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
369+
; CHECK-LABEL: sexti1_i32_setcc:
370+
; CHECK: # %bb.0:
371+
; CHECK-NEXT: srli a0, a0, 31
372+
; CHECK-NEXT: not a0, a0
373+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
374+
; CHECK-NEXT: zext.b a0, a0
375+
; CHECK-NEXT: ret
376+
%icmp = icmp sgt i32 %a, -1
377+
%sext = sext i1 %icmp to i8
378+
ret i8 %sext
379+
}
380+
367381
define i32 @sexti8_i32(i32 %a) {
368382
; CHECK-LABEL: sexti8_i32:
369383
; CHECK: # %bb.0:

‎llvm/test/CodeGen/RISCV/rv32xtheadbb.ll‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -314,6 +314,27 @@ define i32 @sexti1_i32_2(i1 %a) nounwind {
314314
ret i32 %sext
315315
}
316316

317+
; Make sure we don't use not+th.ext
318+
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
319+
; RV32I-LABEL: sexti1_i32_setcc:
320+
; RV32I: # %bb.0:
321+
; RV32I-NEXT: srli a0, a0, 31
322+
; RV32I-NEXT: addi a0, a0, -1
323+
; RV32I-NEXT: zext.b a0, a0
324+
; RV32I-NEXT: ret
325+
;
326+
; RV32XTHEADBB-LABEL: sexti1_i32_setcc:
327+
; RV32XTHEADBB: # %bb.0:
328+
; RV32XTHEADBB-NEXT: srli a0, a0, 31
329+
; RV32XTHEADBB-NEXT: not a0, a0
330+
; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0
331+
; RV32XTHEADBB-NEXT: zext.b a0, a0
332+
; RV32XTHEADBB-NEXT: ret
333+
%icmp = icmp sgt i32 %a, -1
334+
%sext = sext i1 %icmp to i8
335+
ret i8 %sext
336+
}
337+
317338
define i32 @sextb_i32(i32 %a) nounwind {
318339
; RV32I-LABEL: sextb_i32:
319340
; RV32I: # %bb.0:

‎llvm/test/CodeGen/RISCV/rv64xandesperf.ll‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -277,6 +277,20 @@ define signext i32 @sexti1_i32_2(i1 %a) {
277277
ret i32 %1
278278
}
279279

280+
; Make sure we don't use not+nds.bfos
281+
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
282+
; CHECK-LABEL: sexti1_i32_setcc:
283+
; CHECK: # %bb.0:
284+
; CHECK-NEXT: srli a0, a0, 63
285+
; CHECK-NEXT: not a0, a0
286+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
287+
; CHECK-NEXT: zext.b a0, a0
288+
; CHECK-NEXT: ret
289+
%icmp = icmp sgt i32 %a, -1
290+
%sext = sext i1 %icmp to i8
291+
ret i8 %sext
292+
}
293+
280294
define signext i32 @sexti8_i32(i32 signext %a) {
281295
; CHECK-LABEL: sexti8_i32:
282296
; CHECK: # %bb.0:
@@ -334,6 +348,20 @@ define i64 @sexti1_i64_2(i1 %a) {
334348
ret i64 %1
335349
}
336350

351+
; Make sure we don't use not+nds.bfos
352+
define zeroext i8 @sexti1_i64_setcc(i64 %a) {
353+
; CHECK-LABEL: sexti1_i64_setcc:
354+
; CHECK: # %bb.0:
355+
; CHECK-NEXT: srli a0, a0, 63
356+
; CHECK-NEXT: not a0, a0
357+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
358+
; CHECK-NEXT: zext.b a0, a0
359+
; CHECK-NEXT: ret
360+
%icmp = icmp sgt i64 %a, -1
361+
%sext = sext i1 %icmp to i8
362+
ret i8 %sext
363+
}
364+
337365
define i64 @sexti8_i64(i64 %a) {
338366
; CHECK-LABEL: sexti8_i64:
339367
; CHECK: # %bb.0:

‎llvm/test/CodeGen/RISCV/rv64xtheadbb.ll‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -635,6 +635,27 @@ define signext i32 @sexti1_i32_2(i1 %a) nounwind {
635635
ret i32 %sext
636636
}
637637

638+
; Make sure we don't use not+th.ext
639+
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
640+
; RV64I-LABEL: sexti1_i32_setcc:
641+
; RV64I: # %bb.0:
642+
; RV64I-NEXT: srli a0, a0, 63
643+
; RV64I-NEXT: addi a0, a0, -1
644+
; RV64I-NEXT: zext.b a0, a0
645+
; RV64I-NEXT: ret
646+
;
647+
; RV64XTHEADBB-LABEL: sexti1_i32_setcc:
648+
; RV64XTHEADBB: # %bb.0:
649+
; RV64XTHEADBB-NEXT: srli a0, a0, 63
650+
; RV64XTHEADBB-NEXT: not a0, a0
651+
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
652+
; RV64XTHEADBB-NEXT: zext.b a0, a0
653+
; RV64XTHEADBB-NEXT: ret
654+
%icmp = icmp sgt i32 %a, -1
655+
%sext = sext i1 %icmp to i8
656+
ret i8 %sext
657+
}
658+
638659
define i64 @sexti1_i64(i64 %a) nounwind {
639660
; RV64I-LABEL: sexti1_i64:
640661
; RV64I: # %bb.0:
@@ -666,6 +687,27 @@ define i64 @sexti1_i64_2(i1 %a) nounwind {
666687
ret i64 %sext
667688
}
668689

690+
; Make sure we don't use not+th.ext
691+
define zeroext i8 @sexti1_i64_setcc(i64 %a) {
692+
; RV64I-LABEL: sexti1_i64_setcc:
693+
; RV64I: # %bb.0:
694+
; RV64I-NEXT: srli a0, a0, 63
695+
; RV64I-NEXT: addi a0, a0, -1
696+
; RV64I-NEXT: zext.b a0, a0
697+
; RV64I-NEXT: ret
698+
;
699+
; RV64XTHEADBB-LABEL: sexti1_i64_setcc:
700+
; RV64XTHEADBB: # %bb.0:
701+
; RV64XTHEADBB-NEXT: srli a0, a0, 63
702+
; RV64XTHEADBB-NEXT: not a0, a0
703+
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
704+
; RV64XTHEADBB-NEXT: zext.b a0, a0
705+
; RV64XTHEADBB-NEXT: ret
706+
%icmp = icmp sgt i64 %a, -1
707+
%sext = sext i1 %icmp to i8
708+
ret i8 %sext
709+
}
710+
669711
define signext i32 @sextb_i32(i32 signext %a) nounwind {
670712
; RV64I-LABEL: sextb_i32:
671713
; RV64I: # %bb.0:

‎llvm/test/CodeGen/RISCV/xqcibm-extract.ll‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,35 @@ define i32 @sexti1_i32_2(i32 %a) {
4747
ret i32 %shr
4848
}
4949

50+
; Make sure we don't use not+qc.ext
51+
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
52+
; RV32I-LABEL: sexti1_i32_setcc:
53+
; RV32I: # %bb.0:
54+
; RV32I-NEXT: srli a0, a0, 31
55+
; RV32I-NEXT: addi a0, a0, -1
56+
; RV32I-NEXT: zext.b a0, a0
57+
; RV32I-NEXT: ret
58+
;
59+
; RV32XQCIBM-LABEL: sexti1_i32_setcc:
60+
; RV32XQCIBM: # %bb.0:
61+
; RV32XQCIBM-NEXT: srli a0, a0, 31
62+
; RV32XQCIBM-NEXT: not a0, a0
63+
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
64+
; RV32XQCIBM-NEXT: qc.extu a0, a0, 8, 0
65+
; RV32XQCIBM-NEXT: ret
66+
;
67+
; RV32XQCIBMZBB-LABEL: sexti1_i32_setcc:
68+
; RV32XQCIBMZBB: # %bb.0:
69+
; RV32XQCIBMZBB-NEXT: srli a0, a0, 31
70+
; RV32XQCIBMZBB-NEXT: not a0, a0
71+
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0
72+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 8, 0
73+
; RV32XQCIBMZBB-NEXT: ret
74+
%icmp = icmp sgt i32 %a, -1
75+
%sext = sext i1 %icmp to i8
76+
ret i8 %sext
77+
}
78+
5079

5180
define i32 @sexti8_i32(i8 %a) nounwind {
5281
; RV32I-LABEL: sexti8_i32:

0 commit comments

Comments
 (0)