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[RISCV] Fold (sext_inreg (setcc), i1) -> (sub 0, (setcc).
This helsp the 3 vendor extensions that make sext_inreg i1 legal. I'm delaying this until after LegalizeDAG since we normally have sext_inreg i1 up until LegalizeDAG turns it into and+neg. I also delayed the recently added (sext_inreg (xor (setcc), -1), i1) combine. Though the xor isn't likely to appear before LegalizeDAG anyway.
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6 files changed

+39
-33
lines changed

6 files changed

+39
-33
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16639,33 +16639,38 @@ static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
1663916639
}
1664016640

1664116641
static SDValue
16642-
performSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
16642+
performSIGN_EXTEND_INREGCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1664316643
const RISCVSubtarget &Subtarget) {
16644+
SelectionDAG &DAG = DCI.DAG;
1664416645
SDValue Src = N->getOperand(0);
1664516646
EVT VT = N->getValueType(0);
1664616647
EVT SrcVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1664716648
unsigned Opc = Src.getOpcode();
16649+
SDLoc DL(N);
1664816650

1664916651
// Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)
1665016652
// Don't do this with Zhinx. We need to explicitly sign extend the GPR.
1665116653
if (Opc == RISCVISD::FMV_X_ANYEXTH && SrcVT.bitsGE(MVT::i16) &&
1665216654
Subtarget.hasStdExtZfhmin())
16653-
return DAG.getNode(RISCVISD::FMV_X_SIGNEXTH, SDLoc(N), VT,
16654-
Src.getOperand(0));
16655+
return DAG.getNode(RISCVISD::FMV_X_SIGNEXTH, DL, VT, Src.getOperand(0));
1665516656

1665616657
// Fold (sext_inreg (shl X, Y), i32) -> (sllw X, Y) iff Y u< 32
1665716658
if (Opc == ISD::SHL && Subtarget.is64Bit() && SrcVT == MVT::i32 &&
1665816659
VT == MVT::i64 && !isa<ConstantSDNode>(Src.getOperand(1)) &&
1665916660
DAG.computeKnownBits(Src.getOperand(1)).countMaxActiveBits() <= 5)
16660-
return DAG.getNode(RISCVISD::SLLW, SDLoc(N), VT, Src.getOperand(0),
16661+
return DAG.getNode(RISCVISD::SLLW, DL, VT, Src.getOperand(0),
1666116662
Src.getOperand(1));
1666216663

16664+
// Fold (sext_inreg (setcc), i1) -> (sub 0, (setcc)
16665+
if (Opc == ISD::SETCC && DCI.isAfterLegalizeDAG())
16666+
return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Src);
16667+
1666316668
// Fold (sext_inreg (xor (setcc), -1), i1) -> (add (setcc), -1)
1666416669
if (Opc == ISD::XOR && SrcVT == MVT::i1 &&
1666516670
isAllOnesConstant(Src.getOperand(1)) &&
16666-
Src.getOperand(0).getOpcode() == ISD::SETCC)
16667-
return DAG.getNode(ISD::ADD, SDLoc(N), VT, Src.getOperand(0),
16668-
DAG.getAllOnesConstant(SDLoc(N), VT));
16671+
Src.getOperand(0).getOpcode() == ISD::SETCC && DCI.isAfterLegalizeDAG())
16672+
return DAG.getNode(ISD::ADD, DL, VT, Src.getOperand(0),
16673+
DAG.getAllOnesConstant(DL, VT));
1666916674

1667016675
return SDValue();
1667116676
}
@@ -20088,7 +20093,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
2008820093
case ISD::SETCC:
2008920094
return performSETCCCombine(N, DAG, Subtarget);
2009020095
case ISD::SIGN_EXTEND_INREG:
20091-
return performSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
20096+
return performSIGN_EXTEND_INREGCombine(N, DCI, Subtarget);
2009220097
case ISD::ZERO_EXTEND:
2009320098
// Fold (zero_extend (fp_to_uint X)) to prevent forming fcvt+zexti32 during
2009420099
// type legalization. This is safe because fp_to_uint produces poison if

‎llvm/test/CodeGen/RISCV/rv32xandesperf.ll‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -382,8 +382,8 @@ define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
382382
; CHECK-LABEL: sexti1_i32_setcc_2:
383383
; CHECK: # %bb.0:
384384
; CHECK-NEXT: xor a0, a0, a1
385-
; CHECK-NEXT: seqz a0, a0
386-
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
385+
; CHECK-NEXT: snez a0, a0
386+
; CHECK-NEXT: addi a0, a0, -1
387387
; CHECK-NEXT: ret
388388
%icmp = icmp eq i32 %a, %b
389389
%sext = sext i1 %icmp to i32
@@ -394,8 +394,9 @@ define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
394394
define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
395395
; CHECK-LABEL: sexti1_i32_setcc_3:
396396
; CHECK: # %bb.0:
397-
; CHECK-NEXT: slt a0, a0, a1
398-
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
397+
; CHECK-NEXT: slt a1, a0, a1
398+
; CHECK-NEXT: li a0, 0
399+
; CHECK-NEXT: sub a0, a0, a1
399400
; CHECK-NEXT: ret
400401
%icmp = icmp slt i32 %a, %b
401402
%sext = sext i1 %icmp to i32

‎llvm/test/CodeGen/RISCV/rv32xtheadbb.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -346,8 +346,8 @@ define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
346346
; RV32XTHEADBB-LABEL: sexti1_i32_setcc_2:
347347
; RV32XTHEADBB: # %bb.0:
348348
; RV32XTHEADBB-NEXT: xor a0, a0, a1
349-
; RV32XTHEADBB-NEXT: seqz a0, a0
350-
; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0
349+
; RV32XTHEADBB-NEXT: snez a0, a0
350+
; RV32XTHEADBB-NEXT: addi a0, a0, -1
351351
; RV32XTHEADBB-NEXT: ret
352352
%icmp = icmp eq i32 %a, %b
353353
%sext = sext i1 %icmp to i32
@@ -365,7 +365,7 @@ define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
365365
; RV32XTHEADBB-LABEL: sexti1_i32_setcc_3:
366366
; RV32XTHEADBB: # %bb.0:
367367
; RV32XTHEADBB-NEXT: slt a0, a0, a1
368-
; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0
368+
; RV32XTHEADBB-NEXT: neg a0, a0
369369
; RV32XTHEADBB-NEXT: ret
370370
%icmp = icmp slt i32 %a, %b
371371
%sext = sext i1 %icmp to i32

‎llvm/test/CodeGen/RISCV/rv64xandesperf.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -295,8 +295,8 @@ define signext i32 @sexti1_i32_setcc_2(i32 signext %a, i32 signext %b) {
295295
; CHECK-LABEL: sexti1_i32_setcc_2:
296296
; CHECK: # %bb.0:
297297
; CHECK-NEXT: xor a0, a0, a1
298-
; CHECK-NEXT: seqz a0, a0
299-
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
298+
; CHECK-NEXT: snez a0, a0
299+
; CHECK-NEXT: addi a0, a0, -1
300300
; CHECK-NEXT: ret
301301
%icmp = icmp eq i32 %a, %b
302302
%sext = sext i1 %icmp to i32
@@ -308,7 +308,7 @@ define signext i32 @sexti1_i32_setcc_3(i32 signext %a, i32 signext %b) {
308308
; CHECK-LABEL: sexti1_i32_setcc_3:
309309
; CHECK: # %bb.0:
310310
; CHECK-NEXT: slt a0, a0, a1
311-
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
311+
; CHECK-NEXT: neg a0, a0
312312
; CHECK-NEXT: ret
313313
%icmp = icmp slt i32 %a, %b
314314
%sext = sext i1 %icmp to i32
@@ -390,8 +390,8 @@ define i64 @sexti1_i64_setcc_2(i64 %a, i64 %b) {
390390
; CHECK-LABEL: sexti1_i64_setcc_2:
391391
; CHECK: # %bb.0:
392392
; CHECK-NEXT: xor a0, a0, a1
393-
; CHECK-NEXT: seqz a0, a0
394-
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
393+
; CHECK-NEXT: snez a0, a0
394+
; CHECK-NEXT: addi a0, a0, -1
395395
; CHECK-NEXT: ret
396396
%icmp = icmp eq i64 %a, %b
397397
%sext = sext i1 %icmp to i64
@@ -403,7 +403,7 @@ define i64 @sexti1_i64_setcc_3(i64 %a, i64 %b) {
403403
; CHECK-LABEL: sexti1_i64_setcc_3:
404404
; CHECK: # %bb.0:
405405
; CHECK-NEXT: slt a0, a0, a1
406-
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
406+
; CHECK-NEXT: neg a0, a0
407407
; CHECK-NEXT: ret
408408
%icmp = icmp slt i64 %a, %b
409409
%sext = sext i1 %icmp to i64

‎llvm/test/CodeGen/RISCV/rv64xtheadbb.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -667,8 +667,8 @@ define signext i32 @sexti1_i32_setcc_2(i32 signext %a, i32 signext %b) {
667667
; RV64XTHEADBB-LABEL: sexti1_i32_setcc_2:
668668
; RV64XTHEADBB: # %bb.0:
669669
; RV64XTHEADBB-NEXT: xor a0, a0, a1
670-
; RV64XTHEADBB-NEXT: seqz a0, a0
671-
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
670+
; RV64XTHEADBB-NEXT: snez a0, a0
671+
; RV64XTHEADBB-NEXT: addi a0, a0, -1
672672
; RV64XTHEADBB-NEXT: ret
673673
%icmp = icmp eq i32 %a, %b
674674
%sext = sext i1 %icmp to i32
@@ -686,7 +686,7 @@ define signext i32 @sexti1_i32_setcc_3(i32 signext %a, i32 signext %b) {
686686
; RV64XTHEADBB-LABEL: sexti1_i32_setcc_3:
687687
; RV64XTHEADBB: # %bb.0:
688688
; RV64XTHEADBB-NEXT: slt a0, a0, a1
689-
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
689+
; RV64XTHEADBB-NEXT: neg a0, a0
690690
; RV64XTHEADBB-NEXT: ret
691691
%icmp = icmp slt i32 %a, %b
692692
%sext = sext i1 %icmp to i32
@@ -756,8 +756,8 @@ define i64 @sexti1_i64_setcc_2(i64 %a, i64 %b) {
756756
; RV64XTHEADBB-LABEL: sexti1_i64_setcc_2:
757757
; RV64XTHEADBB: # %bb.0:
758758
; RV64XTHEADBB-NEXT: xor a0, a0, a1
759-
; RV64XTHEADBB-NEXT: seqz a0, a0
760-
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
759+
; RV64XTHEADBB-NEXT: snez a0, a0
760+
; RV64XTHEADBB-NEXT: addi a0, a0, -1
761761
; RV64XTHEADBB-NEXT: ret
762762
%icmp = icmp eq i64 %a, %b
763763
%sext = sext i1 %icmp to i64
@@ -775,7 +775,7 @@ define i64 @sexti1_i64_setcc_3(i64 %a, i64 %b) {
775775
; RV64XTHEADBB-LABEL: sexti1_i64_setcc_3:
776776
; RV64XTHEADBB: # %bb.0:
777777
; RV64XTHEADBB-NEXT: slt a0, a0, a1
778-
; RV64XTHEADBB-NEXT: th.ext a0, a0, 0, 0
778+
; RV64XTHEADBB-NEXT: neg a0, a0
779779
; RV64XTHEADBB-NEXT: ret
780780
%icmp = icmp slt i64 %a, %b
781781
%sext = sext i1 %icmp to i64

‎llvm/test/CodeGen/RISCV/xqcibm-extract.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -86,15 +86,15 @@ define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
8686
; RV32XQCIBM-LABEL: sexti1_i32_setcc_2:
8787
; RV32XQCIBM: # %bb.0:
8888
; RV32XQCIBM-NEXT: xor a0, a0, a1
89-
; RV32XQCIBM-NEXT: seqz a0, a0
90-
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
89+
; RV32XQCIBM-NEXT: snez a0, a0
90+
; RV32XQCIBM-NEXT: addi a0, a0, -1
9191
; RV32XQCIBM-NEXT: ret
9292
;
9393
; RV32XQCIBMZBB-LABEL: sexti1_i32_setcc_2:
9494
; RV32XQCIBMZBB: # %bb.0:
9595
; RV32XQCIBMZBB-NEXT: xor a0, a0, a1
96-
; RV32XQCIBMZBB-NEXT: seqz a0, a0
97-
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0
96+
; RV32XQCIBMZBB-NEXT: snez a0, a0
97+
; RV32XQCIBMZBB-NEXT: addi a0, a0, -1
9898
; RV32XQCIBMZBB-NEXT: ret
9999
%icmp = icmp eq i32 %a, %b
100100
%sext = sext i1 %icmp to i32
@@ -112,13 +112,13 @@ define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
112112
; RV32XQCIBM-LABEL: sexti1_i32_setcc_3:
113113
; RV32XQCIBM: # %bb.0:
114114
; RV32XQCIBM-NEXT: slt a0, a0, a1
115-
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
115+
; RV32XQCIBM-NEXT: neg a0, a0
116116
; RV32XQCIBM-NEXT: ret
117117
;
118118
; RV32XQCIBMZBB-LABEL: sexti1_i32_setcc_3:
119119
; RV32XQCIBMZBB: # %bb.0:
120120
; RV32XQCIBMZBB-NEXT: slt a0, a0, a1
121-
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0
121+
; RV32XQCIBMZBB-NEXT: neg a0, a0
122122
; RV32XQCIBMZBB-NEXT: ret
123123
%icmp = icmp slt i32 %a, %b
124124
%sext = sext i1 %icmp to i32

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