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[TableGen][DecoderEmitter] Inline insertBits() (NFC) (#159353)
`tmp` is always of integer type, so we can use bitwise OR and shift.
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5 files changed

+18
-28
lines changed

5 files changed

+18
-28
lines changed

llvm/include/llvm/MC/MCDecoder.h

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -58,20 +58,6 @@ uint64_t fieldFromInstruction(const std::bitset<N> &Insn, unsigned StartBit,
5858
return ((Insn >> StartBit) & Mask).to_ullong();
5959
}
6060

61-
// Helper function for inserting bits extracted from an encoded instruction into
62-
// an integer-typed field.
63-
template <typename IntType>
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static std::enable_if_t<std::is_integral_v<IntType>, void>
65-
insertBits(IntType &field, IntType bits, unsigned startBit, unsigned numBits) {
66-
// Check that no bit beyond numBits is set, so that a simple bitwise |
67-
// is sufficient.
68-
assert((~(((IntType)1 << numBits) - 1) & bits) == 0 &&
69-
"bits has more than numBits bits set");
70-
assert(startBit + numBits <= sizeof(IntType) * 8);
71-
(void)numBits;
72-
field |= bits << startBit;
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}
74-
7561
} // namespace llvm::MCD
7662

7763
#endif // LLVM_MC_MCDECODER_H

llvm/test/TableGen/BitOffsetDecoder.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,6 @@ def baz : Instruction {
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// CHECK: tmp = fieldFromInstruction(insn, 8, 7);
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// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 3;
62-
// CHECK: insertBits(tmp, fieldFromInstruction(insn, 8, 4), 7, 4);
63-
// CHECK: insertBits(tmp, fieldFromInstruction(insn, 12, 4), 3, 4);
62+
// CHECK: tmp |= fieldFromInstruction(insn, 8, 4) << 7;
63+
// CHECK: tmp |= fieldFromInstruction(insn, 12, 4) << 3;
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// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 4;

llvm/test/TableGen/DecoderEmitter/VarLenDecoder.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,8 @@ def FOO32 : MyVarInst<MemOp32> {
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);
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// CHECK-NEXT: if (!Check(S, myCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = 0x0;
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// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 11, 16), 16, 16);
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// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 27, 16), 0, 16);
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 11, 16) << 16;
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// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 27, 16);
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: return S;
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llvm/test/TableGen/DecoderEmitter/operand-decoder.td

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -17,25 +17,25 @@ def MyTarget : Target {
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 2, 4);
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x0;
20-
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 0, 2), 0, 2);
21-
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 6, 2), 2, 2);
20+
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 0, 2);
21+
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 6, 2) << 2;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x0;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 13, 2) << 1;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x0;
28-
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 17, 1), 1, 1);
29-
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 19, 1), 3, 1);
28+
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 17, 1) << 1;
29+
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 19, 1) << 3;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x5;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0x2;
34-
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 26, 2), 2, 2);
34+
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 26, 2) << 2;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: tmp = 0xa;
37-
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 28, 1), 0, 1);
38-
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 30, 1), 2, 1);
37+
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 28, 1);
38+
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 30, 1) << 2;
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
4040
// CHECK-NEXT: return S;
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llvm/utils/TableGen/DecoderEmitter.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1041,9 +1041,13 @@ static void emitBinaryParser(raw_ostream &OS, indent Indent,
10411041
// insert the variable parts into it.
10421042
OS << Indent << "tmp = " << format_hex(OpInfo.InitValue.value_or(0), 0)
10431043
<< ";\n";
1044-
for (auto [Base, Width, Offset] : OpInfo.fields())
1045-
OS << Indent << "insertBits(tmp, fieldFromInstruction(insn, " << Base
1046-
<< ", " << Width << "), " << Offset << ", " << Width << ");\n";
1044+
for (auto [Base, Width, Offset] : OpInfo.fields()) {
1045+
OS << Indent << "tmp |= fieldFromInstruction(insn, " << Base << ", "
1046+
<< Width << ')';
1047+
if (Offset)
1048+
OS << " << " << Offset;
1049+
OS << ";\n";
1050+
}
10471051
}
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10491053
StringRef Decoder = OpInfo.Decoder;

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