@@ -612,13 +612,10 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
612612 // Collect the SPIRVTypes for fp16, fp32, and fp64 and the constant of
613613 // type int32 with 0 value to represent the FP Fast Math Mode.
614614 std::vector<const MachineInstr *> SPIRVFloatTypes;
615- const MachineInstr *ConstZero = nullptr ;
615+ const MachineInstr *ConstZeroInt32 = nullptr ;
616616 for (const MachineInstr *MI :
617617 MAI->getMSInstrs (SPIRV::MB_TypeConstVars)) {
618- // Skip if the instruction is not OpTypeFloat or OpConstant.
619618 unsigned OpCode = MI->getOpcode ();
620- if (OpCode != SPIRV::OpTypeFloat && OpCode != SPIRV::OpConstantNull)
621- continue ;
622619
623620 // Collect the SPIRV type if it's a float.
624621 if (OpCode == SPIRV::OpTypeFloat) {
@@ -629,17 +626,19 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
629626 continue ;
630627 }
631628 SPIRVFloatTypes.push_back (MI);
632- } else {
629+ continue ;
630+ }
631+
632+ if (OpCode == SPIRV::OpConstantNull) {
633633 // Check if the constant is int32, if not skip it.
634634 const MachineRegisterInfo &MRI = MI->getMF ()->getRegInfo ();
635635 MachineInstr *TypeMI = MRI.getVRegDef (MI->getOperand (1 ).getReg ());
636636 bool IsInt32Ty = TypeMI &&
637637 TypeMI->getOpcode () == SPIRV::OpTypeInt &&
638638 TypeMI->getOperand (1 ).getImm () == 32 ;
639- if (!IsInt32Ty)
640- continue ;
641-
642- ConstZero = MI;
639+ if (IsInt32Ty)
640+ ConstZeroInt32 = MI;
641+ continue ;
643642 }
644643 }
645644
@@ -660,9 +659,9 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
660659 MCRegister TypeReg =
661660 MAI->getRegisterAlias (MF, MI->getOperand (0 ).getReg ());
662661 Inst.addOperand (MCOperand::createReg (TypeReg));
663- assert (ConstZero && " There should be a constant zero." );
662+ assert (ConstZeroInt32 && " There should be a constant zero." );
664663 MCRegister ConstReg = MAI->getRegisterAlias (
665- ConstZero ->getMF (), ConstZero ->getOperand (0 ).getReg ());
664+ ConstZeroInt32 ->getMF (), ConstZeroInt32 ->getOperand (0 ).getReg ());
666665 Inst.addOperand (MCOperand::createReg (ConstReg));
667666 outputMCInst (Inst);
668667 }
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