Remove flag; this is now the default scheduler behavior

Author: lucas-rami

llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

@@ -124,9 +124,6 @@ namespace llvm {
     /// rescheduling).
     bool RemoveKillFlags;
 
-    /// True if regions with a single MI should be scheduled.
-    bool ScheduleSingleMIRegions = false;
-
     /// The standard DAG builder does not normally include terminators as DAG
     /// nodes because it does not create the necessary dependencies to prevent
     /// reordering. A specialized scheduler can override
@@ -291,11 +288,6 @@ namespace llvm {
       return Topo.IsReachable(SU, TargetSU);
     }
 
-    /// Whether regions with a single MI should be scheduled.
-    bool shouldScheduleSingleMIRegions() const {
-      return ScheduleSingleMIRegions;
-    }
-
     /// Returns an iterator to the top of the current scheduling region.
     MachineBasicBlock::iterator begin() const { return RegionBegin; }
 

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -770,7 +770,6 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
 
     MBBRegionsVector MBBRegions;
     getSchedRegions(&*MBB, MBBRegions, Scheduler.doMBBSchedRegionsTopDown());
-    bool ScheduleSingleMI = Scheduler.shouldScheduleSingleMIRegions();
     for (const SchedRegion &R : MBBRegions) {
       MachineBasicBlock::iterator I = R.RegionBegin;
       MachineBasicBlock::iterator RegionEnd = R.RegionEnd;
@@ -781,7 +780,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
       Scheduler.enterRegion(&*MBB, I, RegionEnd, NumRegionInstrs);
 
       // Skip empty scheduling regions (0 or 1 schedulable instructions).
-      if (I == RegionEnd || (!ScheduleSingleMI && I == std::prev(RegionEnd))) {
+      if (I == RegionEnd) {
         // Close the current region. Bundle the terminator if needed.
         // This invalidates 'RegionEnd' and 'I'.
         Scheduler.exitRegion();

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -759,10 +759,7 @@ GCNScheduleDAGMILive::GCNScheduleDAGMILive(
       MFI(*MF.getInfo<SIMachineFunctionInfo>()),
       StartingOccupancy(MFI.getOccupancy()), MinOccupancy(StartingOccupancy),
       RegionLiveOuts(this, /*IsLiveOut=*/true) {
-  // We want regions with a single MI to be scheduled so that we can reason on
-  // them correctly during scheduling stages that move MIs between regions (e.g.
-  // rematerialization).
-  ScheduleSingleMIRegions = true;
+
   LLVM_DEBUG(dbgs() << "Starting occupancy is " << StartingOccupancy << ".\n");
   if (RelaxedOcc) {
     MinOccupancy = std::min(MFI.getMinAllowedOccupancy(), StartingOccupancy);

llvm/test/CodeGen/ARM/misched-branch-targets.mir

@@ -1,7 +1,7 @@
-# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
-# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck %s
-# RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
-# RUN: llc -o - -passes=postmisched %s | FileCheck %s
+# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck -check-prefixes=CHECK,CHECK-MISCHED %s
+# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck -check-prefixes=CHECK,CHECK-MISCHED %s
+# RUN: llc -o - -run-pass=postmisched %s | FileCheck -check-prefixes=CHECK,CHECK-POSTMISCHED %s
+# RUN: llc -o - -passes=postmisched %s | FileCheck -check-prefixes=CHECK,CHECK-POSTMISCHED %s
 
 # REQUIRES: asserts
 # -misched=shuffle is only available with assertions enabled
@@ -147,7 +147,8 @@ body:             |
 
 # CHECK-LABEL: name:            foo_setjmp
 # CHECK:       body:
-# CHECK:         tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
+# CHECK-MISCHED:         tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def $r0
+# CHECK-POSTMISCHED:     tBL 14 /* CC::al */, $noreg, @setjmp, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
 # CHECK-NEXT:    t2BTI
 
 ---

llvm/test/CodeGen/PowerPC/pr47155-47156.ll

@@ -4,6 +4,7 @@
 ; RUN:   -stop-after=postmisched -debug-only=machine-scheduler 2>&1 >/dev/null | FileCheck %s
 
 define void @pr47155() {
+; CHECK-LABEL: Machine code for function pr47155
 ; CHECK: *** Final schedule for %bb.0 ***
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-NEXT: pr47155:%bb.0 entry
@@ -23,6 +24,7 @@ entry:
 }
 
 define void @pr47156(ptr %fn) {
+; CHECK-LABEL: Machine code for function pr47156
 ; CHECK: *** Final schedule for %bb.0 ***
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-NEXT: pr47156:%bb.0 entry

llvm/test/CodeGen/X86/fake-use-scheduler.mir

@@ -9,6 +9,12 @@
 #
 # CHECK: ********** MI Scheduling **********
 # CHECK-NEXT: foo:%bb.0 entry
+# CHECK-NEXT:   From: $rax = COPY %5:gr64
+# CHECK-NEXT:     To: RET 0, killed $rax
+# CHECK-NEXT:  RegionInstrs: 1
+#
+# CHECK: ********** MI Scheduling **********
+# CHECK-NEXT: foo:%bb.0 entry
 # CHECK-NEXT:   From: %0:gr64 = COPY $rdi
 # CHECK-NEXT:     To: FAKE_USE %5:gr64
 # CHECK-NEXT:  RegionInstrs: 7