@@ -228,6 +228,24 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
228228 SubReg0 = SubReg1;
229229 }
230230
231+ // For a case like this:
232+ // %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
233+ // we need to update the implicit-def after commuting to result in:
234+ // %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
235+ SmallVector<unsigned > UpdateImplicitDefIdx;
236+ if (HasDef && MI.hasImplicitDef () && MI.getOperand (0 ).getReg () != Reg0) {
237+ const TargetRegisterInfo *TRI =
238+ MI.getMF ()->getSubtarget ().getRegisterInfo ();
239+ Register OrigReg0 = MI.getOperand (0 ).getReg ();
240+ for (auto [OpNo, MO] : llvm::enumerate (MI.implicit_operands ())) {
241+ Register ImplReg = MO.getReg ();
242+ if ((ImplReg.isVirtual () && ImplReg == OrigReg0) ||
243+ (ImplReg.isPhysical () && OrigReg0.isPhysical () &&
244+ TRI->isSubRegisterEq (ImplReg, OrigReg0)))
245+ UpdateImplicitDefIdx.push_back (OpNo + MI.getNumExplicitOperands ());
246+ }
247+ }
248+
231249 MachineInstr *CommutedMI = nullptr ;
232250 if (NewMI) {
233251 // Create a new instruction.
@@ -238,15 +256,10 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
238256 }
239257
240258 if (HasDef) {
241- // Use `substituteRegister` so that for a case like this:
242- // %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
243- // the implicit-def is also updated, to result in:
244- // %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
245- const TargetRegisterInfo &TRI =
246- *MI.getMF ()->getSubtarget ().getRegisterInfo ();
247- Register FromReg = CommutedMI->getOperand (0 ).getReg ();
248- CommutedMI->substituteRegister (FromReg, Reg0, /* SubRegIdx=*/ 0 , TRI);
259+ CommutedMI->getOperand (0 ).setReg (Reg0);
249260 CommutedMI->getOperand (0 ).setSubReg (SubReg0);
261+ for (unsigned Idx : UpdateImplicitDefIdx)
262+ CommutedMI->getOperand (Idx).setReg (Reg0);
250263 }
251264 CommutedMI->getOperand (Idx2).setReg (Reg1);
252265 CommutedMI->getOperand (Idx1).setReg (Reg2);
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