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[RISCV] Allow constants in tryFoldSelectIntoOp (#157376)
For simm12 constants this allows the use of e.g. addi/xori, and for non-simm12 constants seems to still produce better code than the default lowering.
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3 files changed

+73
-124
lines changed

3 files changed

+73
-124
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18838,7 +18838,7 @@ static SDValue tryFoldSelectIntoOp(SDNode *N, SelectionDAG &DAG,
1883818838
break;
1883918839
}
1884018840

18841-
if (!TrueVal.hasOneUse() || isa<ConstantSDNode>(FalseVal))
18841+
if (!TrueVal.hasOneUse())
1884218842
return SDValue();
1884318843

1884418844
unsigned OpToFold;

‎llvm/test/CodeGen/RISCV/select.ll‎

Lines changed: 63 additions & 112 deletions
Original file line numberDiff line numberDiff line change
@@ -290,38 +290,28 @@ entry:
290290
define i32 @select_xor_5(i1 zeroext %cond, i32 %x) {
291291
; RV32IM-LABEL: select_xor_5:
292292
; RV32IM: # %bb.0:
293-
; RV32IM-NEXT: bnez a0, .LBB8_2
294-
; RV32IM-NEXT: # %bb.1:
295-
; RV32IM-NEXT: xori a0, a1, 128
296-
; RV32IM-NEXT: ret
297-
; RV32IM-NEXT: .LBB8_2:
298-
; RV32IM-NEXT: li a0, 128
293+
; RV32IM-NEXT: addi a0, a0, -1
294+
; RV32IM-NEXT: and a0, a0, a1
295+
; RV32IM-NEXT: xori a0, a0, 128
299296
; RV32IM-NEXT: ret
300297
;
301298
; RV64IM-LABEL: select_xor_5:
302299
; RV64IM: # %bb.0:
303-
; RV64IM-NEXT: bnez a0, .LBB8_2
304-
; RV64IM-NEXT: # %bb.1:
305-
; RV64IM-NEXT: xori a0, a1, 128
306-
; RV64IM-NEXT: ret
307-
; RV64IM-NEXT: .LBB8_2:
308-
; RV64IM-NEXT: li a0, 128
300+
; RV64IM-NEXT: addi a0, a0, -1
301+
; RV64IM-NEXT: and a0, a0, a1
302+
; RV64IM-NEXT: xori a0, a0, 128
309303
; RV64IM-NEXT: ret
310304
;
311305
; RV64IMXVTCONDOPS-LABEL: select_xor_5:
312306
; RV64IMXVTCONDOPS: # %bb.0:
313-
; RV64IMXVTCONDOPS-NEXT: xori a1, a1, 128
314-
; RV64IMXVTCONDOPS-NEXT: addi a1, a1, -128
315307
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
316-
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 128
308+
; RV64IMXVTCONDOPS-NEXT: xori a0, a0, 128
317309
; RV64IMXVTCONDOPS-NEXT: ret
318310
;
319311
; CHECKZICOND-LABEL: select_xor_5:
320312
; CHECKZICOND: # %bb.0:
321-
; CHECKZICOND-NEXT: xori a1, a1, 128
322-
; CHECKZICOND-NEXT: addi a1, a1, -128
323313
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
324-
; CHECKZICOND-NEXT: addi a0, a0, 128
314+
; CHECKZICOND-NEXT: xori a0, a0, 128
325315
; CHECKZICOND-NEXT: ret
326316
%add = xor i32 %x, 128
327317
%sel = select i1 %cond, i32 128, i32 %add
@@ -643,38 +633,28 @@ entry:
643633
define i32 @select_or_4(i1 zeroext %cond, i32 %x) {
644634
; RV32IM-LABEL: select_or_4:
645635
; RV32IM: # %bb.0:
646-
; RV32IM-NEXT: bnez a0, .LBB17_2
647-
; RV32IM-NEXT: # %bb.1:
648-
; RV32IM-NEXT: ori a0, a1, 128
649-
; RV32IM-NEXT: ret
650-
; RV32IM-NEXT: .LBB17_2:
651-
; RV32IM-NEXT: li a0, 128
636+
; RV32IM-NEXT: addi a0, a0, -1
637+
; RV32IM-NEXT: and a0, a0, a1
638+
; RV32IM-NEXT: ori a0, a0, 128
652639
; RV32IM-NEXT: ret
653640
;
654641
; RV64IM-LABEL: select_or_4:
655642
; RV64IM: # %bb.0:
656-
; RV64IM-NEXT: bnez a0, .LBB17_2
657-
; RV64IM-NEXT: # %bb.1:
658-
; RV64IM-NEXT: ori a0, a1, 128
659-
; RV64IM-NEXT: ret
660-
; RV64IM-NEXT: .LBB17_2:
661-
; RV64IM-NEXT: li a0, 128
643+
; RV64IM-NEXT: addi a0, a0, -1
644+
; RV64IM-NEXT: and a0, a0, a1
645+
; RV64IM-NEXT: ori a0, a0, 128
662646
; RV64IM-NEXT: ret
663647
;
664648
; RV64IMXVTCONDOPS-LABEL: select_or_4:
665649
; RV64IMXVTCONDOPS: # %bb.0:
666-
; RV64IMXVTCONDOPS-NEXT: ori a1, a1, 128
667-
; RV64IMXVTCONDOPS-NEXT: addi a1, a1, -128
668650
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
669-
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 128
651+
; RV64IMXVTCONDOPS-NEXT: ori a0, a0, 128
670652
; RV64IMXVTCONDOPS-NEXT: ret
671653
;
672654
; CHECKZICOND-LABEL: select_or_4:
673655
; CHECKZICOND: # %bb.0:
674-
; CHECKZICOND-NEXT: ori a1, a1, 128
675-
; CHECKZICOND-NEXT: addi a1, a1, -128
676656
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
677-
; CHECKZICOND-NEXT: addi a0, a0, 128
657+
; CHECKZICOND-NEXT: ori a0, a0, 128
678658
; CHECKZICOND-NEXT: ret
679659
%add = or i32 %x, 128
680660
%sel = select i1 %cond, i32 128, i32 %add
@@ -801,30 +781,22 @@ entry:
801781
define i32 @select_add_4(i1 zeroext %cond, i32 %x) {
802782
; RV32IM-LABEL: select_add_4:
803783
; RV32IM: # %bb.0:
804-
; RV32IM-NEXT: bnez a0, .LBB21_2
805-
; RV32IM-NEXT: # %bb.1:
806-
; RV32IM-NEXT: addi a0, a1, 128
807-
; RV32IM-NEXT: ret
808-
; RV32IM-NEXT: .LBB21_2:
809-
; RV32IM-NEXT: li a0, 128
784+
; RV32IM-NEXT: addi a0, a0, -1
785+
; RV32IM-NEXT: and a0, a0, a1
786+
; RV32IM-NEXT: addi a0, a0, 128
810787
; RV32IM-NEXT: ret
811788
;
812789
; RV64IM-LABEL: select_add_4:
813790
; RV64IM: # %bb.0:
814-
; RV64IM-NEXT: bnez a0, .LBB21_2
815-
; RV64IM-NEXT: # %bb.1:
816-
; RV64IM-NEXT: addiw a0, a1, 128
817-
; RV64IM-NEXT: ret
818-
; RV64IM-NEXT: .LBB21_2:
819-
; RV64IM-NEXT: li a0, 128
791+
; RV64IM-NEXT: addi a0, a0, -1
792+
; RV64IM-NEXT: and a0, a0, a1
793+
; RV64IM-NEXT: addiw a0, a0, 128
820794
; RV64IM-NEXT: ret
821795
;
822796
; RV64IMXVTCONDOPS-LABEL: select_add_4:
823797
; RV64IMXVTCONDOPS: # %bb.0:
824-
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, 128
825-
; RV64IMXVTCONDOPS-NEXT: addi a1, a1, -128
826798
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
827-
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 128
799+
; RV64IMXVTCONDOPS-NEXT: addiw a0, a0, 128
828800
; RV64IMXVTCONDOPS-NEXT: ret
829801
;
830802
; RV32IMZICOND-LABEL: select_add_4:
@@ -835,10 +807,8 @@ define i32 @select_add_4(i1 zeroext %cond, i32 %x) {
835807
;
836808
; RV64IMZICOND-LABEL: select_add_4:
837809
; RV64IMZICOND: # %bb.0:
838-
; RV64IMZICOND-NEXT: addiw a1, a1, 128
839-
; RV64IMZICOND-NEXT: addi a1, a1, -128
840810
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
841-
; RV64IMZICOND-NEXT: addi a0, a0, 128
811+
; RV64IMZICOND-NEXT: addiw a0, a0, 128
842812
; RV64IMZICOND-NEXT: ret
843813
%add = add i32 %x, 128
844814
%sel = select i1 %cond, i32 128, i32 %add
@@ -848,26 +818,19 @@ define i32 @select_add_4(i1 zeroext %cond, i32 %x) {
848818
define i64 @select_add_5(i1 zeroext %cond, i64 %x) {
849819
; RV32IM-LABEL: select_add_5:
850820
; RV32IM: # %bb.0:
851-
; RV32IM-NEXT: addi a3, a1, 128
852-
; RV32IM-NEXT: sltu a1, a3, a1
853-
; RV32IM-NEXT: add a2, a2, a1
854-
; RV32IM-NEXT: beqz a0, .LBB22_2
855-
; RV32IM-NEXT: # %bb.1:
856-
; RV32IM-NEXT: li a3, 128
857-
; RV32IM-NEXT: .LBB22_2:
858-
; RV32IM-NEXT: addi a0, a0, -1
859-
; RV32IM-NEXT: and a1, a0, a2
860-
; RV32IM-NEXT: mv a0, a3
821+
; RV32IM-NEXT: addi a3, a0, -1
822+
; RV32IM-NEXT: and a1, a3, a1
823+
; RV32IM-NEXT: addi a0, a1, 128
824+
; RV32IM-NEXT: sltu a1, a0, a1
825+
; RV32IM-NEXT: and a2, a3, a2
826+
; RV32IM-NEXT: add a1, a2, a1
861827
; RV32IM-NEXT: ret
862828
;
863829
; RV64IM-LABEL: select_add_5:
864830
; RV64IM: # %bb.0:
865-
; RV64IM-NEXT: bnez a0, .LBB22_2
866-
; RV64IM-NEXT: # %bb.1:
867-
; RV64IM-NEXT: addi a0, a1, 128
868-
; RV64IM-NEXT: ret
869-
; RV64IM-NEXT: .LBB22_2:
870-
; RV64IM-NEXT: li a0, 128
831+
; RV64IM-NEXT: addi a0, a0, -1
832+
; RV64IM-NEXT: and a0, a0, a1
833+
; RV64IM-NEXT: addi a0, a0, 128
871834
; RV64IM-NEXT: ret
872835
;
873836
; RV64IMXVTCONDOPS-LABEL: select_add_5:
@@ -878,12 +841,12 @@ define i64 @select_add_5(i1 zeroext %cond, i64 %x) {
878841
;
879842
; RV32IMZICOND-LABEL: select_add_5:
880843
; RV32IMZICOND: # %bb.0:
844+
; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
881845
; RV32IMZICOND-NEXT: addi a3, a1, 128
882-
; RV32IMZICOND-NEXT: sltu a3, a3, a1
883-
; RV32IMZICOND-NEXT: czero.nez a4, a1, a0
884-
; RV32IMZICOND-NEXT: add a2, a2, a3
885-
; RV32IMZICOND-NEXT: czero.nez a1, a2, a0
886-
; RV32IMZICOND-NEXT: addi a0, a4, 128
846+
; RV32IMZICOND-NEXT: sltu a1, a3, a1
847+
; RV32IMZICOND-NEXT: czero.nez a0, a2, a0
848+
; RV32IMZICOND-NEXT: add a1, a0, a1
849+
; RV32IMZICOND-NEXT: mv a0, a3
887850
; RV32IMZICOND-NEXT: ret
888851
;
889852
; RV64IMZICOND-LABEL: select_add_5:
@@ -899,63 +862,51 @@ define i64 @select_add_5(i1 zeroext %cond, i64 %x) {
899862
define i64 @select_add_6(i1 zeroext %cond, i64 %x) {
900863
; RV32IM-LABEL: select_add_6:
901864
; RV32IM: # %bb.0:
902-
; RV32IM-NEXT: lui a3, 14
903-
; RV32IM-NEXT: addi a3, a3, 1005
904-
; RV32IM-NEXT: add a4, a1, a3
905-
; RV32IM-NEXT: sltu a1, a4, a1
906-
; RV32IM-NEXT: add a2, a2, a1
907-
; RV32IM-NEXT: bnez a0, .LBB23_2
908-
; RV32IM-NEXT: # %bb.1:
909-
; RV32IM-NEXT: mv a3, a4
910-
; RV32IM-NEXT: .LBB23_2:
911-
; RV32IM-NEXT: addi a0, a0, -1
912-
; RV32IM-NEXT: and a1, a0, a2
913-
; RV32IM-NEXT: mv a0, a3
865+
; RV32IM-NEXT: addi a3, a0, -1
866+
; RV32IM-NEXT: lui a0, 14
867+
; RV32IM-NEXT: and a1, a3, a1
868+
; RV32IM-NEXT: addi a0, a0, 1005
869+
; RV32IM-NEXT: add a0, a1, a0
870+
; RV32IM-NEXT: sltu a1, a0, a1
871+
; RV32IM-NEXT: and a2, a3, a2
872+
; RV32IM-NEXT: add a1, a2, a1
914873
; RV32IM-NEXT: ret
915874
;
916875
; RV64IM-LABEL: select_add_6:
917876
; RV64IM: # %bb.0:
918-
; RV64IM-NEXT: mv a2, a0
919-
; RV64IM-NEXT: lui a0, 14
920-
; RV64IM-NEXT: addi a0, a0, 1005
921-
; RV64IM-NEXT: bnez a2, .LBB23_2
922-
; RV64IM-NEXT: # %bb.1:
923-
; RV64IM-NEXT: add a0, a1, a0
924-
; RV64IM-NEXT: .LBB23_2:
877+
; RV64IM-NEXT: addi a0, a0, -1
878+
; RV64IM-NEXT: and a0, a0, a1
879+
; RV64IM-NEXT: lui a1, 14
880+
; RV64IM-NEXT: addi a1, a1, 1005
881+
; RV64IM-NEXT: add a0, a0, a1
925882
; RV64IM-NEXT: ret
926883
;
927884
; RV64IMXVTCONDOPS-LABEL: select_add_6:
928885
; RV64IMXVTCONDOPS: # %bb.0:
929-
; RV64IMXVTCONDOPS-NEXT: lui a2, 14
930-
; RV64IMXVTCONDOPS-NEXT: addi a2, a2, 1005
931-
; RV64IMXVTCONDOPS-NEXT: add a1, a1, a2
932-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a2, a2, a0
933886
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
934-
; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0
887+
; RV64IMXVTCONDOPS-NEXT: lui a1, 14
888+
; RV64IMXVTCONDOPS-NEXT: addi a1, a1, 1005
889+
; RV64IMXVTCONDOPS-NEXT: add a0, a0, a1
935890
; RV64IMXVTCONDOPS-NEXT: ret
936891
;
937892
; RV32IMZICOND-LABEL: select_add_6:
938893
; RV32IMZICOND: # %bb.0:
894+
; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
939895
; RV32IMZICOND-NEXT: lui a3, 14
940896
; RV32IMZICOND-NEXT: addi a3, a3, 1005
941-
; RV32IMZICOND-NEXT: add a4, a1, a3
942-
; RV32IMZICOND-NEXT: czero.eqz a3, a3, a0
943-
; RV32IMZICOND-NEXT: sltu a1, a4, a1
944-
; RV32IMZICOND-NEXT: czero.nez a4, a4, a0
945-
; RV32IMZICOND-NEXT: add a1, a2, a1
946-
; RV32IMZICOND-NEXT: or a2, a3, a4
947-
; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
948-
; RV32IMZICOND-NEXT: mv a0, a2
897+
; RV32IMZICOND-NEXT: add a3, a1, a3
898+
; RV32IMZICOND-NEXT: sltu a1, a3, a1
899+
; RV32IMZICOND-NEXT: czero.nez a0, a2, a0
900+
; RV32IMZICOND-NEXT: add a1, a0, a1
901+
; RV32IMZICOND-NEXT: mv a0, a3
949902
; RV32IMZICOND-NEXT: ret
950903
;
951904
; RV64IMZICOND-LABEL: select_add_6:
952905
; RV64IMZICOND: # %bb.0:
953-
; RV64IMZICOND-NEXT: lui a2, 14
954-
; RV64IMZICOND-NEXT: addi a2, a2, 1005
955-
; RV64IMZICOND-NEXT: add a1, a1, a2
956-
; RV64IMZICOND-NEXT: czero.eqz a2, a2, a0
957906
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
958-
; RV64IMZICOND-NEXT: or a0, a2, a0
907+
; RV64IMZICOND-NEXT: lui a1, 14
908+
; RV64IMZICOND-NEXT: addi a1, a1, 1005
909+
; RV64IMZICOND-NEXT: add a0, a0, a1
959910
; RV64IMZICOND-NEXT: ret
960911
%add = add i64 %x, 58349
961912
%sel = select i1 %cond, i64 58349, i64 %add

‎llvm/test/CodeGen/RISCV/zicond-opts.ll‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -223,11 +223,10 @@ define i64 @test_inv_and_nez(i64 %f, i64 %x, i1 %cond) {
223223
; RV32ZICOND-LABEL: test_inv_and_nez:
224224
; RV32ZICOND: # %bb.0:
225225
; RV32ZICOND-NEXT: andi a4, a4, 1
226-
; RV32ZICOND-NEXT: addi a4, a4, -1
227-
; RV32ZICOND-NEXT: orn a3, a4, a3
228-
; RV32ZICOND-NEXT: orn a2, a4, a2
229-
; RV32ZICOND-NEXT: and a0, a2, a0
230-
; RV32ZICOND-NEXT: and a1, a3, a1
226+
; RV32ZICOND-NEXT: czero.eqz a3, a3, a4
227+
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
228+
; RV32ZICOND-NEXT: andn a0, a0, a2
229+
; RV32ZICOND-NEXT: andn a1, a1, a3
231230
; RV32ZICOND-NEXT: ret
232231
;
233232
; RV64ZICOND-LABEL: test_inv_and_nez:
@@ -246,12 +245,11 @@ define i64 @test_inv_and_nez(i64 %f, i64 %x, i1 %cond) {
246245
define i64 @test_inv_and_eqz(i64 %f, i64 %x, i1 %cond) {
247246
; RV32ZICOND-LABEL: test_inv_and_eqz:
248247
; RV32ZICOND: # %bb.0:
249-
; RV32ZICOND-NEXT: slli a4, a4, 31
250-
; RV32ZICOND-NEXT: srai a4, a4, 31
251-
; RV32ZICOND-NEXT: orn a3, a4, a3
252-
; RV32ZICOND-NEXT: orn a2, a4, a2
253-
; RV32ZICOND-NEXT: and a0, a2, a0
254-
; RV32ZICOND-NEXT: and a1, a3, a1
248+
; RV32ZICOND-NEXT: andi a4, a4, 1
249+
; RV32ZICOND-NEXT: czero.nez a3, a3, a4
250+
; RV32ZICOND-NEXT: czero.nez a2, a2, a4
251+
; RV32ZICOND-NEXT: andn a0, a0, a2
252+
; RV32ZICOND-NEXT: andn a1, a1, a3
255253
; RV32ZICOND-NEXT: ret
256254
;
257255
; RV64ZICOND-LABEL: test_inv_and_eqz:

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