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[AMDGPU][MC] Avoid creating lit64() operands unless asked or needed.
There should normally be no need to generate implicit lit64() modifiers on the assembler side. It's the encoder's responsibility to recognise literals that are implicitly 64 bits wide. The exceptions are where we rewrite floating-point operand values as integer ones, which would not be assembled back to the original values unless wrapped into lit64(). Respect explicit lit() modifiers for non-inline values as necessary to avoid regressions in MC tests. This change still doesn't prevent use of inline constants where lit()/lit64 is specified; subject to a separate patch. On disassembling, only create lit64() operands where necessary for correct round-tripping. Add round-tripping tests where useful and feasible.
1 parent 668f56d commit dba6718

24 files changed

+428
-387
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 47 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2330,6 +2330,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23302330
bool CanUse64BitLiterals =
23312331
AsmParser->has64BitLiterals() &&
23322332
!(InstDesc.TSFlags & (SIInstrFlags::VOP3 | SIInstrFlags::VOP3P));
2333+
LitModifier Lit = getModifiers().Lit;
23332334
MCContext &Ctx = AsmParser->getContext();
23342335

23352336
if (Imm.IsFPImm) { // We got fp literal token
@@ -2363,10 +2364,23 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23632364

23642365
if ((OpTy == AMDGPU::OPERAND_REG_IMM_FP64 ||
23652366
OpTy == AMDGPU::OPERAND_REG_INLINE_C_FP64 ||
2366-
OpTy == AMDGPU::OPERAND_REG_INLINE_AC_FP64) &&
2367-
CanUse64BitLiterals && Lo_32(Val) != 0) {
2368-
Inst.addOperand(MCOperand::createExpr(
2369-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2367+
OpTy == AMDGPU::OPERAND_REG_INLINE_AC_FP64)) {
2368+
if (CanUse64BitLiterals && Lit == LitModifier::None &&
2369+
(isInt<32>(Val) || isUInt<32>(Val))) {
2370+
// The floating-point operand will be verbalized as an
2371+
// integer one. If that integer happens to fit 32 bits, on
2372+
// re-assembling it will be intepreted as the high half of
2373+
// the actual value, so we have to wrap it into lit64().
2374+
Lit = LitModifier::Lit64;
2375+
} else if (Lit == LitModifier::Lit) {
2376+
// For FP64 operands lit() specifies the high half of the value.
2377+
Val = Hi_32(Val);
2378+
}
2379+
}
2380+
2381+
if (Lit != LitModifier::None) {
2382+
Inst.addOperand(
2383+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
23702384
} else {
23712385
Inst.addOperand(MCOperand::createImm(Val));
23722386
}
@@ -2379,9 +2393,13 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23792393
llvm_unreachable("fp literal in 64-bit integer instruction.");
23802394

23812395
case AMDGPU::OPERAND_KIMM64:
2382-
if (CanUse64BitLiterals && Lo_32(Val) != 0) {
2383-
Inst.addOperand(MCOperand::createExpr(
2384-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2396+
if (CanUse64BitLiterals && Lit == LitModifier::None &&
2397+
(isInt<32>(Val) || isUInt<32>(Val)))
2398+
Lit = LitModifier::Lit64;
2399+
2400+
if (Lit != LitModifier::None) {
2401+
Inst.addOperand(
2402+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
23852403
} else {
23862404
Inst.addOperand(MCOperand::createImm(Val));
23872405
}
@@ -2470,13 +2488,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24702488
// truncated to uint32_t), if the target doesn't support 64-bit literals, or
24712489
// the lit modifier is explicitly used, we need to truncate it to the 32
24722490
// LSBs.
2473-
if (!AsmParser->has64BitLiterals() ||
2474-
getModifiers().Lit == LitModifier::Lit)
2491+
if (!AsmParser->has64BitLiterals() || Lit == LitModifier::Lit)
24752492
Val = Lo_32(Val);
24762493

2477-
if (CanUse64BitLiterals && (!isInt<32>(Val) || !isUInt<32>(Val))) {
2478-
Inst.addOperand(MCOperand::createExpr(
2479-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2494+
if (Lit != LitModifier::None) {
2495+
Inst.addOperand(
2496+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
24802497
} else {
24812498
Inst.addOperand(MCOperand::createImm(Val));
24822499
}
@@ -2500,15 +2517,18 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
25002517
// 1) explicitly forced by using lit modifier;
25012518
// 2) the value is a valid 32-bit representation (signed or unsigned),
25022519
// meanwhile not forced by lit64 modifier.
2503-
if (getModifiers().Lit == LitModifier::Lit ||
2504-
(getModifiers().Lit != LitModifier::Lit64 &&
2505-
(isInt<32>(Val) || isUInt<32>(Val))))
2520+
if (Lit == LitModifier::Lit ||
2521+
(Lit != LitModifier::Lit64 && (isInt<32>(Val) || isUInt<32>(Val))))
25062522
Val = static_cast<uint64_t>(Val) << 32;
25072523
}
25082524

2509-
if (CanUse64BitLiterals && Lo_32(Val) != 0) {
2510-
Inst.addOperand(MCOperand::createExpr(
2511-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2525+
// For FP64 operands lit() specifies the high half of the value.
2526+
if (Lit == LitModifier::Lit)
2527+
Val = Hi_32(Val);
2528+
2529+
if (Lit != LitModifier::None) {
2530+
Inst.addOperand(
2531+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
25122532
} else {
25132533
Inst.addOperand(MCOperand::createImm(Val));
25142534
}
@@ -2529,13 +2549,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
25292549
return;
25302550

25312551
case AMDGPU::OPERAND_KIMM64:
2532-
if ((isInt<32>(Val) || isUInt<32>(Val)) &&
2533-
getModifiers().Lit != LitModifier::Lit64)
2552+
if ((isInt<32>(Val) || isUInt<32>(Val)) && Lit != LitModifier::Lit64)
25342553
Val <<= 32;
25352554

2536-
if (CanUse64BitLiterals && Lo_32(Val) != 0) {
2537-
Inst.addOperand(MCOperand::createExpr(
2538-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2555+
if (Lit != LitModifier::None) {
2556+
Inst.addOperand(
2557+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
25392558
} else {
25402559
Inst.addOperand(MCOperand::createImm(Val));
25412560
}
@@ -4813,12 +4832,15 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst,
48134832
const MCOperand &MO = Inst.getOperand(OpIdx);
48144833
// Exclude special imm operands (like that used by s_set_gpr_idx_on)
48154834
if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {
4835+
bool IsLit = false;
48164836
std::optional<int64_t> Imm;
48174837
if (MO.isImm()) {
48184838
Imm = MO.getImm();
48194839
} else if (MO.isExpr()) {
4820-
if (isLitExpr(MO.getExpr()))
4840+
if (isLitExpr(MO.getExpr())) {
4841+
IsLit = true;
48214842
Imm = getLitValue(MO.getExpr());
4843+
}
48224844
} else {
48234845
continue;
48244846
}
@@ -4828,7 +4850,7 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst,
48284850
} else if (!isInlineConstant(Inst, OpIdx)) {
48294851
auto OpType = static_cast<AMDGPU::OperandType>(
48304852
Desc.operands()[OpIdx].OperandType);
4831-
int64_t Value = encode32BitLiteral(*Imm, OpType);
4853+
int64_t Value = encode32BitLiteral(*Imm, OpType, IsLit);
48324854
if (NumLiterals == 0 || LiteralValue != Value) {
48334855
LiteralValue = Value;
48344856
++NumLiterals;

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1545,7 +1545,7 @@ AMDGPUDisassembler::decodeMandatoryLiteral64Constant(uint64_t Val) const {
15451545
HasLiteral = true;
15461546
Literal = Literal64 = Val;
15471547

1548-
bool UseLit64 = Lo_32(Literal64) != 0;
1548+
bool UseLit64 = Hi_32(Literal64) == 0;
15491549
return UseLit64 ? MCOperand::createExpr(AMDGPUMCExpr::createLit(
15501550
LitModifier::Lit64, Literal64, getContext()))
15511551
: MCOperand::createImm(Literal64);
@@ -1578,11 +1578,11 @@ MCOperand AMDGPUDisassembler::decodeLiteralConstant(const MCInstrDesc &Desc,
15781578
if (CanUse64BitLiterals) {
15791579
if (OpDesc.OperandType == AMDGPU::OPERAND_REG_IMM_INT64 ||
15801580
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT64)
1581-
UseLit64 = !isInt<32>(Val) || !isUInt<32>(Val);
1581+
UseLit64 = false;
15821582
else if (OpDesc.OperandType == AMDGPU::OPERAND_REG_IMM_FP64 ||
15831583
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_C_FP64 ||
15841584
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_AC_FP64)
1585-
UseLit64 = Lo_32(Val) != 0;
1585+
UseLit64 = Hi_32(Literal64) == 0;
15861586
}
15871587

15881588
return UseLit64 ? MCOperand::createExpr(AMDGPUMCExpr::createLit(
@@ -1608,12 +1608,12 @@ AMDGPUDisassembler::decodeLiteral64Constant(const MCInst &Inst) const {
16081608
const MCOperandInfo &OpDesc = Desc.operands()[Inst.getNumOperands()];
16091609
if (OpDesc.OperandType == AMDGPU::OPERAND_REG_IMM_INT64 ||
16101610
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT64) {
1611-
UseLit64 = !isInt<32>(Literal64) || !isUInt<32>(Literal64);
1611+
UseLit64 = false;
16121612
} else {
16131613
assert(OpDesc.OperandType == AMDGPU::OPERAND_REG_IMM_FP64 ||
16141614
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_C_FP64 ||
16151615
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_AC_FP64);
1616-
UseLit64 = Lo_32(Literal64) != 0;
1616+
UseLit64 = Hi_32(Literal64) == 0;
16171617
}
16181618

16191619
return UseLit64 ? MCOperand::createExpr(AMDGPUMCExpr::createLit(

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -452,13 +452,16 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
452452
// Yes! Encode it
453453
int64_t Imm = 0;
454454

455+
bool IsLit = false;
455456
if (Op.isImm())
456457
Imm = Op.getImm();
457458
else if (Op.isExpr()) {
458-
if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
459+
if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr())) {
459460
Imm = C->getValue();
460-
else if (AMDGPU::isLitExpr(Op.getExpr()))
461+
} else if (AMDGPU::isLitExpr(Op.getExpr())) {
462+
IsLit = true;
461463
Imm = AMDGPU::getLitValue(Op.getExpr());
464+
}
462465
} else // Exprs will be replaced with a fixup value.
463466
llvm_unreachable("Must be immediate or expr");
464467

@@ -468,7 +471,7 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
468471
} else {
469472
auto OpType =
470473
static_cast<AMDGPU::OperandType>(Desc.operands()[i].OperandType);
471-
Imm = AMDGPU::encode32BitLiteral(Imm, OpType);
474+
Imm = AMDGPU::encode32BitLiteral(Imm, OpType, IsLit);
472475
support::endian::write<uint32_t>(CB, Imm, llvm::endianness::little);
473476
}
474477

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3157,7 +3157,7 @@ bool isValid32BitLiteral(uint64_t Val, bool IsFP64) {
31573157
return isUInt<32>(Val) || isInt<32>(Val);
31583158
}
31593159

3160-
int64_t encode32BitLiteral(int64_t Imm, OperandType Type) {
3160+
int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit) {
31613161
switch (Type) {
31623162
default:
31633163
break;
@@ -3180,7 +3180,7 @@ int64_t encode32BitLiteral(int64_t Imm, OperandType Type) {
31803180
case OPERAND_REG_INLINE_C_INT32:
31813181
return Lo_32(Imm);
31823182
case OPERAND_REG_IMM_FP64:
3183-
return Hi_32(Imm);
3183+
return IsLit ? Imm : Hi_32(Imm);
31843184
}
31853185
return Imm;
31863186
}

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1724,7 +1724,7 @@ LLVM_READNONE
17241724
bool isValid32BitLiteral(uint64_t Val, bool IsFP64);
17251725

17261726
LLVM_READNONE
1727-
int64_t encode32BitLiteral(int64_t Imm, OperandType Type);
1727+
int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit);
17281728

17291729
bool isArgPassedInSGPR(const Argument *Arg);
17301730

‎llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s‎

Lines changed: 28 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1,64 +1,70 @@
1-
// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s
1+
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
2+
// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefixes=GFX1250,GFX1250-ASM %s
3+
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250,GFX1250-DIS %s
24

35
s_mov_b64 s[2:3], 0x10abcdef12345678
4-
// GFX1250: s_mov_b64 s[2:3], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
6+
// GFX1250: s_mov_b64 s[2:3], 0x10abcdef12345678 ; encoding: [0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
57

68
s_add_nc_u64 s[2:3], s[4:5], 0x10abcdef12345678
7-
// GFX1250: s_add_nc_u64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
9+
// GFX1250: s_add_nc_u64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
810

911
s_mul_u64 s[2:3], 0x10abcdef12345678, s[4:5]
10-
// GFX1250: s_mul_u64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
12+
// GFX1250: s_mul_u64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
1113

1214
s_and_b64 s[2:3], 0x10abcdef12345678, s[4:5]
13-
// GFX1250: s_and_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
15+
// GFX1250: s_and_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
1416

1517
s_or_b64 s[2:3], s[4:5], 0x10abcdef12345678
16-
// GFX1250: s_or_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
18+
// GFX1250: s_or_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
1719

1820
s_xor_b64 s[2:3], 0x10abcdef12345678, s[4:5]
19-
// GFX1250: s_xor_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
21+
// GFX1250: s_xor_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
2022

2123
s_and_not1_b64 s[2:3], 0x10abcdef12345678, 0x10abcdef12345678
22-
// GFX1250: s_and_not1_b64 s[2:3], lit64(0x10abcdef12345678), lit64(0x10abcdef12345678) ; encoding: [0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
24+
// GFX1250: s_and_not1_b64 s[2:3], 0x10abcdef12345678, 0x10abcdef12345678 ; encoding: [0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
2325

2426
s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678
25-
// GFX1250: s_or_not1_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
27+
// GFX1250: s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
2628

2729
s_andn2_b64 s[2:3], 0x10abcdef12345678, s[4:5]
28-
// GFX1250: s_and_not1_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
30+
// GFX1250: s_and_not1_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
2931

3032
s_orn2_b64 s[2:3], s[4:5], 0x10abcdef12345678
31-
// GFX1250: s_or_not1_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
33+
// GFX1250: s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
3234

3335
s_nand_b64 s[2:3], s[4:5], 0x10abcdef12345678
34-
// GFX1250: s_nand_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
36+
// GFX1250: s_nand_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
3537

3638
s_nor_b64 s[2:3], s[4:5], 0x10abcdef12345678
37-
// GFX1250: s_nor_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
39+
// GFX1250: s_nor_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
3840

3941
s_xnor_b64 s[2:3], s[4:5], 0x10abcdef12345678
40-
// GFX1250: s_xnor_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
42+
// GFX1250: s_xnor_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
4143

4244
s_lshl_b64 s[2:3], 0x10abcdef12345678, s4
43-
// GFX1250: s_lshl_b64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
45+
// GFX1250: s_lshl_b64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
4446

4547
s_lshr_b64 s[2:3], 0x10abcdef12345678, s4
46-
// GFX1250: s_lshr_b64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
48+
// GFX1250: s_lshr_b64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
4749

4850
s_ashr_i64 s[2:3], 0x10abcdef12345678, s4
49-
// GFX1250: s_ashr_i64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
51+
// GFX1250: s_ashr_i64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
5052

5153
s_bfe_u64 s[2:3], 0x10abcdef12345678, 5
52-
// GFX1250: s_bfe_u64 s[2:3], lit64(0x10abcdef12345678), 5 ; encoding: [0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
54+
// GFX1250: s_bfe_u64 s[2:3], 0x10abcdef12345678, 5 ; encoding: [0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
5355

5456
s_bfe_i64 s[2:3], 0x80abcdef12345678, 5
55-
// GFX1250: s_bfe_i64 s[2:3], lit64(0x80abcdef12345678), 5 ; encoding: [0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80]
57+
// GFX1250: s_bfe_i64 s[2:3], 0x80abcdef12345678, 5 ; encoding: [0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80]
5658

5759
s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678
58-
// GFX1250: s_cselect_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
60+
// GFX1250: s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
5961

6062
s_mov_b64 s[2:3], 0xffffffff01234567
61-
// GFX1250: s_mov_b64 s[2:3], lit64(0xffffffff01234567) ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff]
63+
// GFX1250: s_mov_b64 s[2:3], 0xffffffff01234567 ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff]
6264

6365
s_mov_b64 s[2:3], lit64(0x777)
64-
// GFX1250: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
66+
// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
67+
// GFX1250-DIS: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
68+
69+
s_mov_b64 s[2:3], 0x777
70+
// GFX1250: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]

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