[RISCV] Refactor SelectAddrRegRegScale. NFC

Rename UnwrapShl->SelectShl. Make it only responsible for matching
a SHL by constant.

Handle the fallback case of reg+reg with no scale outside of SelectShl.

Reorder the check so RHS is checked for shift first. The base pointer
is most likely on the LHS. It's very unlikely both operands are shifts.

This is preparation for adding better costing decisions to this code.

Author: topperc

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -3038,49 +3038,61 @@ bool RISCVDAGToDAGISel::SelectAddrRegRegScale(SDValue Addr,
                                               SDValue &Scale) {
   if (Addr.getOpcode() != ISD::ADD)
     return false;
+  SDValue LHS = Addr.getOperand(0);
+  SDValue RHS = Addr.getOperand(1);
 
   EVT VT = Addr.getSimpleValueType();
-  auto UnwrapShl = [this, VT, MaxShiftAmount](SDValue N, SDValue &Index,
+  auto SelectShl = [this, VT, MaxShiftAmount](SDValue N, SDValue &Index,
                                               SDValue &Shift) {
-    uint64_t ShiftAmt = 0;
-    Index = N;
-
-    if (N.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N.getOperand(1))) {
-      // Only match shifts by a value in range [0, MaxShiftAmount].
-      if (N.getConstantOperandVal(1) <= MaxShiftAmount) {
-        Index = N.getOperand(0);
-        ShiftAmt = N.getConstantOperandVal(1);
-      }
-    }
+    if (N.getOpcode() != ISD::SHL || !isa<ConstantSDNode>(N.getOperand(1)))
+      return false;
+
+    // Only match shifts by a value in range [0, MaxShiftAmount].
+    unsigned ShiftAmt = N.getConstantOperandVal(1);
+    if (ShiftAmt > MaxShiftAmount)
+      return false;
 
+    Index = N.getOperand(0);
     Shift = CurDAG->getTargetConstant(ShiftAmt, SDLoc(N), VT);
-    return ShiftAmt != 0;
+    return true;
   };
 
-  if (auto *C1 = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
-    SDValue AddrB = Addr.getOperand(0);
-    if (AddrB.getOpcode() == ISD::ADD &&
-        UnwrapShl(AddrB.getOperand(0), Index, Scale) &&
-        !isa<ConstantSDNode>(AddrB.getOperand(1)) &&
+  if (auto *C1 = dyn_cast<ConstantSDNode>(RHS)) {
+    if (LHS.getOpcode() == ISD::ADD &&
+        SelectShl(LHS.getOperand(0), Index, Scale) &&
+        !isa<ConstantSDNode>(LHS.getOperand(1)) &&
         isInt<12>(C1->getSExtValue())) {
       // (add (add (shl A C2) B) C1) -> (add (add B C1) (shl A C2))
       SDValue C1Val = CurDAG->getTargetConstant(*C1->getConstantIntValue(),
                                                 SDLoc(Addr), VT);
       Base = SDValue(CurDAG->getMachineNode(RISCV::ADDI, SDLoc(Addr), VT,
-                                            AddrB.getOperand(1), C1Val),
+                                            LHS.getOperand(1), C1Val),
                      0);
       return true;
     }
-  } else if (UnwrapShl(Addr.getOperand(0), Index, Scale)) {
-    Base = Addr.getOperand(1);
+
+    // Don't match add with constants.
+    // FIXME: Is this profitable for large constants that have 0s in the lower
+    // 12 bits that we can materialize with LUI?
+    return false;
+  }
+
+  // Try to match a shift on the RHS.
+  if (SelectShl(RHS, Index, Scale)) {
+    Base = LHS;
     return true;
-  } else {
-    UnwrapShl(Addr.getOperand(1), Index, Scale);
-    Base = Addr.getOperand(0);
+  }
+
+  // Try to match a shift on the LHS.
+  if (SelectShl(LHS, Index, Scale)) {
+    Base = RHS;
     return true;
   }
 
-  return false;
+  Base = LHS;
+  Index = RHS;
+  Scale = CurDAG->getTargetConstant(0, SDLoc(Addr), VT);
+  return true;
 }
 
 bool RISCVDAGToDAGISel::SelectAddrRegReg(SDValue Addr, SDValue &Base,