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[AMDGPU] Simplify VT comparisons. NFC. (#169526)
Automated with `sed -i 's/\.Value//g' lib/Target/AMDGPU/*.td` plus a tiny bit of manual reformatting.
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 51 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ def mfma_f32_32x32x64_f8f6f4 : UnscaledMFMAOptimizationPat<int_amdgcn_mfma_scale
326326
//===----------------------------------------------------------------------===//
327327

328328
class isIntType<ValueType SrcVT> {
329-
bit ret = !and(SrcVT.isInteger, !ne(SrcVT.Value, i1.Value));
329+
bit ret = !and(SrcVT.isInteger, !ne(SrcVT, i1));
330330
}
331331

332332
def SDTSBufferPrefetch : SDTypeProfile<0, 3,
@@ -1787,10 +1787,10 @@ class SIMCInstr <string pseudo, int subtarget> {
17871787

17881788
class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
17891789
int ret =
1790-
!if (!eq(Src0.Value, untyped.Value), 0,
1791-
!if (!eq(Src1.Value, untyped.Value), 1, // VOP1
1792-
!if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1793-
3))); // VOP3
1790+
!if (!eq(Src0, untyped), 0,
1791+
!if (!eq(Src1, untyped), 1, // VOP1
1792+
!if (!eq(Src2, untyped), 2, // VOP2
1793+
3))); // VOP3
17941794
}
17951795

17961796
// Returns the register class to use for the destination of VOP[123C]
@@ -1859,17 +1859,17 @@ class getVCSrcForVT<ValueType VT> {
18591859
!if(VT.isFP,
18601860
!if(!eq(VT.Size, 64),
18611861
VCSrc_f64,
1862-
!cond(!eq(VT.Value, f16.Value) : VCSrc_f16,
1863-
!eq(VT.Value, bf16.Value) : VCSrc_bf16,
1864-
!eq(VT.Value, v2f16.Value) : VCSrc_v2f16,
1865-
!eq(VT.Value, v2bf16.Value) : VCSrc_v2bf16,
1862+
!cond(!eq(VT, f16) : VCSrc_f16,
1863+
!eq(VT, bf16) : VCSrc_bf16,
1864+
!eq(VT, v2f16) : VCSrc_v2f16,
1865+
!eq(VT, v2bf16) : VCSrc_v2bf16,
18661866
1 : VCSrc_f32)
18671867
),
18681868
!if(!eq(VT.Size, 64),
18691869
VCSrc_b64,
1870-
!if(!eq(VT.Value, i16.Value),
1870+
!if(!eq(VT, i16),
18711871
VCSrc_b16,
1872-
!if(!eq(VT.Value, v2i16.Value),
1872+
!if(!eq(VT, v2i16),
18731873
VCSrc_v2b16,
18741874
VCSrc_b32
18751875
)
@@ -1994,28 +1994,28 @@ class getVOP3DPPSrcForVT<ValueType VT, bit IsFake16 = 1> {
19941994

19951995
// Float or packed int
19961996
class isModifierType<ValueType SrcVT> {
1997-
bit ret = !or(!eq(SrcVT.Value, f16.Value),
1998-
!eq(SrcVT.Value, bf16.Value),
1999-
!eq(SrcVT.Value, f32.Value),
2000-
!eq(SrcVT.Value, f64.Value),
2001-
!eq(SrcVT.Value, v2f16.Value),
2002-
!eq(SrcVT.Value, v2i16.Value),
2003-
!eq(SrcVT.Value, v2bf16.Value),
2004-
!eq(SrcVT.Value, v2f32.Value),
2005-
!eq(SrcVT.Value, v2i32.Value),
2006-
!eq(SrcVT.Value, v4f16.Value),
2007-
!eq(SrcVT.Value, v4i16.Value),
2008-
!eq(SrcVT.Value, v4bf16.Value),
2009-
!eq(SrcVT.Value, v4f32.Value),
2010-
!eq(SrcVT.Value, v4i32.Value),
2011-
!eq(SrcVT.Value, v8f16.Value),
2012-
!eq(SrcVT.Value, v8i16.Value),
2013-
!eq(SrcVT.Value, v8bf16.Value),
2014-
!eq(SrcVT.Value, v8f32.Value),
2015-
!eq(SrcVT.Value, v8i32.Value),
2016-
!eq(SrcVT.Value, v16f16.Value),
2017-
!eq(SrcVT.Value, v16i16.Value),
2018-
!eq(SrcVT.Value, v16bf16.Value));
1997+
bit ret = !or(!eq(SrcVT, f16),
1998+
!eq(SrcVT, bf16),
1999+
!eq(SrcVT, f32),
2000+
!eq(SrcVT, f64),
2001+
!eq(SrcVT, v2f16),
2002+
!eq(SrcVT, v2i16),
2003+
!eq(SrcVT, v2bf16),
2004+
!eq(SrcVT, v2f32),
2005+
!eq(SrcVT, v2i32),
2006+
!eq(SrcVT, v4f16),
2007+
!eq(SrcVT, v4i16),
2008+
!eq(SrcVT, v4bf16),
2009+
!eq(SrcVT, v4f32),
2010+
!eq(SrcVT, v4i32),
2011+
!eq(SrcVT, v8f16),
2012+
!eq(SrcVT, v8i16),
2013+
!eq(SrcVT, v8bf16),
2014+
!eq(SrcVT, v8f32),
2015+
!eq(SrcVT, v8i32),
2016+
!eq(SrcVT, v16f16),
2017+
!eq(SrcVT, v16i16),
2018+
!eq(SrcVT, v16bf16));
20192019
}
20202020

20212021
// Return type of input modifiers operand for specified input operand.
@@ -2048,9 +2048,9 @@ class getSrcModDPP <ValueType VT> {
20482048
class getSrcModDPP_t16 <ValueType VT, bit IsFake16 = 1> {
20492049
Operand ret =
20502050
!if (VT.isFP,
2051-
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
2051+
!if (!or(!eq(VT, f16), !eq(VT, bf16)),
20522052
FPT16_Lo128VRegInputMods<IsFake16>, FPVRegInputMods),
2053-
!if (!eq(VT.Value, i16.Value),
2053+
!if (!eq(VT, i16),
20542054
IntT16_Lo128VRegInputMods<IsFake16>, IntVRegInputMods));
20552055
}
20562056

@@ -2059,11 +2059,11 @@ class getSrcModDPP_t16 <ValueType VT, bit IsFake16 = 1> {
20592059
class getSrcModVOP3VC <ValueType VT, bit IsFake16 = 1> {
20602060
Operand ret =
20612061
!if (VT.isFP,
2062-
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
2062+
!if (!or(!eq(VT, f16), !eq(VT, bf16)),
20632063
FPT16VCSrcInputMods<IsFake16>,
2064-
!if (!eq(VT.Value, f64.Value), FP64VCSrcInputMods,
2064+
!if (!eq(VT, f64), FP64VCSrcInputMods,
20652065
FP32VCSrcInputMods)),
2066-
!if (!eq(VT.Value, i16.Value),
2066+
!if (!eq(VT, i16),
20672067
IntT16VCSrcInputMods<IsFake16>,
20682068
Int32VCSrcInputMods));
20692069
}
@@ -2075,15 +2075,15 @@ class getSrcModVOP3VC <ValueType VT, bit IsFake16 = 1> {
20752075
class getSrc0ModVOP3DPP <ValueType VT, ValueType DstVT, bit IsFake16 = 1> {
20762076
defvar T16Dst =
20772077
!if (VT.isFP,
2078-
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
2078+
!if (!or(!eq(VT, f16), !eq(VT, bf16)),
20792079
FPT16VRegInputMods<IsFake16>, FPVRegT16DstInputMods),
2080-
!if (!eq(VT.Value, i16.Value), IntT16VRegInputMods<IsFake16>,
2080+
!if (!eq(VT, i16), IntT16VRegInputMods<IsFake16>,
20812081
IntVRegT16DstInputMods));
20822082
defvar Normal =
20832083
!if (VT.isFP,
2084-
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
2084+
!if (!or(!eq(VT, f16), !eq(VT, bf16)),
20852085
FPT16VRegInputMods<IsFake16>, FPVRegInputMods),
2086-
!if (!eq(VT.Value, i16.Value),
2086+
!if (!eq(VT, i16),
20872087
IntT16VRegInputMods<IsFake16>,
20882088
IntVRegInputMods));
20892089
Operand ret = !if(!and(!not(IsFake16), !eq(DstVT.Size, 16)), T16Dst, Normal);
@@ -2093,16 +2093,16 @@ class getSrc0ModVOP3DPP <ValueType VT, ValueType DstVT, bit IsFake16 = 1> {
20932093
// only operands (VOPD3 vsrc1 and vsrc2).
20942094
class getSrcModVOP3V <ValueType VT> {
20952095
Operand ret =
2096-
!if (!eq(VT.Value, f64.Value), FP64VRegSrcInputMods,
2096+
!if (!eq(VT, f64), FP64VRegSrcInputMods,
20972097
FP32VRegSrcInputMods);
20982098
}
20992099

21002100
// Return type of input modifiers operand specified input operand for SDWA
21012101
class getSrcModSDWA <ValueType VT> {
2102-
Operand ret = !if(!eq(VT.Value, f16.Value), FP16SDWAInputMods,
2103-
!if(!eq(VT.Value, f32.Value), FP32SDWAInputMods,
2104-
!if(!eq(VT.Value, i16.Value), Int16SDWAInputMods,
2105-
!if(!eq(VT.Value, bf16.Value), FP16SDWAInputMods,
2102+
Operand ret = !if(!eq(VT, f16), FP16SDWAInputMods,
2103+
!if(!eq(VT, f32), FP32SDWAInputMods,
2104+
!if(!eq(VT, i16), Int16SDWAInputMods,
2105+
!if(!eq(VT, bf16), FP16SDWAInputMods,
21062106
Int32SDWAInputMods))));
21072107
}
21082108

@@ -2769,14 +2769,14 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
27692769
field bit HasFP8ByteSel = !or(HasFP8SrcByteSel, HasFP8DstByteSel);
27702770
field bit HasBitOp3 = 0;
27712771

2772-
field bit HasDst = !ne(DstVT.Value, untyped.Value);
2772+
field bit HasDst = !ne(DstVT, untyped);
27732773
field bit HasDst32 = HasDst;
27742774
field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case
27752775
field bit EmitDstSel = EmitDst;
27762776
field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
2777-
field bit HasSrc0 = !ne(Src0VT.Value, untyped.Value);
2778-
field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value);
2779-
field bit HasSrc2 = !ne(Src2VT.Value, untyped.Value);
2777+
field bit HasSrc0 = !ne(Src0VT, untyped);
2778+
field bit HasSrc1 = !ne(Src1VT, untyped);
2779+
field bit HasSrc2 = !ne(Src2VT, untyped);
27802780

27812781
field bit HasSrc0FloatMods = Src0VT.isFP;
27822782
field bit HasSrc1FloatMods = Src1VT.isFP;

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ class getInterp16Ins <bit HasSrc2, bit HasOMod,
151151

152152
class VOP3_INTERP16 <list<ValueType> ArgVT, bit OpSel = 0> : VOPProfile<ArgVT> {
153153
let IsSingle = 1;
154-
let HasOMod = !ne(DstVT.Value, f16.Value);
154+
let HasOMod = !ne(DstVT, f16);
155155
let HasHigh = 1;
156156
let HasOpSel = OpSel;
157157

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