Reorder includes

Signed-off-by: Mikhail R. Gadelha <[email protected]>

Author: mikhailramalho

llvm/lib/Target/RISCV/RISCV.td

@@ -52,12 +52,12 @@ include "RISCVSchedSiFive7.td"
 include "RISCVSchedSiFiveP400.td"
 include "RISCVSchedSiFiveP500.td"
 include "RISCVSchedSiFiveP600.td"
+include "RISCVSchedSpacemitX60.td"
 include "RISCVSchedSyntacoreSCR1.td"
 include "RISCVSchedSyntacoreSCR345.td"
 include "RISCVSchedSyntacoreSCR7.td"
 include "RISCVSchedTTAscalonD8.td"
 include "RISCVSchedXiangShanNanHu.td"
-include "RISCVSchedSpacemitX60.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.