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[AMDGPU] Remove Dwarf encodings for subregisters (#117891)
Previously, registers and subregisters mapped to the same Dwarf encoding. We don't really have any way to refer to subregisters directly from Dwarf, the expression emitter should instead use DW_OPs to stencil out the subregister from the whole register. This was also confusing tools that need to map back to the llvm reg (e.g. dwarfdump), since getLLVMRegNum() would arbitrarily return the _LO16 register.
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+61
-29
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4 files changed

+61
-29
lines changed

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -153,14 +153,16 @@ class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
153153
}
154154

155155
multiclass SIRegLoHi16 <string n, bits<8> regIdx, bit ArtificialHigh = 1,
156-
bit isVGPR = 0, bit isAGPR = 0> {
156+
bit isVGPR = 0, bit isAGPR = 0,
157+
list<int> DwarfEncodings = [-1, -1]> {
157158
def _LO16 : SIReg<n#".l", regIdx, isVGPR, isAGPR>;
158159
def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isVGPR, isAGPR,
159160
/* isHi16 */ 1> {
160161
let isArtificial = ArtificialHigh;
161162
}
162163
def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),
163-
!cast<Register>(NAME#"_HI16")]> {
164+
!cast<Register>(NAME#"_HI16")]>,
165+
DwarfRegNum<DwarfEncodings> {
164166
let Namespace = "AMDGPU";
165167
let SubRegIndices = [lo16, hi16];
166168
let CoveredBySubRegs = !not(ArtificialHigh);
@@ -197,7 +199,8 @@ def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
197199
let HWEncoding = VCC_LO.HWEncoding;
198200
}
199201

200-
defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>;
202+
defm EXEC_LO : SIRegLoHi16<"exec_lo", 126, /*ArtificialHigh=*/1, /*isVGPR=*/0,
203+
/*isAGPR=*/0, /*DwarfEncodings=*/[1, 1]>;
201204
defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>;
202205

203206
def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
@@ -337,25 +340,26 @@ def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
337340
// SGPR registers
338341
foreach Index = 0...105 in {
339342
defm SGPR#Index :
340-
SIRegLoHi16 <"s"#Index, Index>,
341-
DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
342-
!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
343+
SIRegLoHi16 <"s"#Index, Index, /*ArtificialHigh=*/1,
344+
/*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/
345+
[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
346+
!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
343347
}
344348

345349
// VGPR registers
346350
foreach Index = 0...255 in {
347351
defm VGPR#Index :
348-
SIRegLoHi16 <"v"#Index, Index, /* ArtificialHigh= */ 0,
349-
/* isVGPR= */ 1, /* isAGPR= */ 0>,
350-
DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>;
352+
SIRegLoHi16 <"v"#Index, Index, /*ArtificialHigh=*/ 0,
353+
/*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/
354+
[!add(Index, 2560), !add(Index, 1536)]>;
351355
}
352356

353357
// AccVGPR registers
354358
foreach Index = 0...255 in {
355359
defm AGPR#Index :
356-
SIRegLoHi16 <"a"#Index, Index, /* ArtificialHigh= */ 1,
357-
/* isVGPR= */ 0, /* isAGPR= */ 1>,
358-
DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>;
360+
SIRegLoHi16 <"a"#Index, Index, /*ArtificialHigh=*/ 1,
361+
/*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/
362+
[!add(Index, 3072), !add(Index, 2048)]>;
359363
}
360364

361365
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ body: |
6767
; GCN-NEXT: {{ $}}
6868
; GCN-NEXT: S_WAITCNT 0
6969
; GCN-NEXT: $vgpr0 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec
70-
; GCN-NEXT: CFI_INSTRUCTION offset $vgpr0_lo16, 16
70+
; GCN-NEXT: CFI_INSTRUCTION offset $vgpr0, 16
7171
$vgpr0 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec
7272
CFI_INSTRUCTION offset $vgpr0, 16
7373

‎llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,11 @@ TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {
5151
// PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
5252
// S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
5353
// A0 => 3072, A255 => 3327
54-
for (int llvmReg : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
55-
MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
56-
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
57-
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true));
54+
for (int DwarfEncoding :
55+
{16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
56+
MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);
57+
EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));
58+
EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));
5859
}
5960
}
6061
}
@@ -70,10 +71,11 @@ TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
7071
// PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
7172
// S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
7273
// A0 => 2048, A255 => 2303
73-
for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
74-
MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
75-
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
76-
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true));
74+
for (int DwarfEncoding :
75+
{16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
76+
MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);
77+
EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));
78+
EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));
7779
}
7880
}
7981
}

‎llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp‎

Lines changed: 34 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -25,11 +25,24 @@ TEST(AMDGPU, TestWave64DwarfRegMapping) {
2525
// PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
2626
// S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
2727
// A0 => 3072, A255 => 3327
28-
for (int llvmReg :
28+
for (int DwarfEncoding :
2929
{16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
30-
MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
31-
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
32-
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true));
30+
MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);
31+
EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));
32+
EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));
33+
}
34+
35+
// We should get the correct LLVM register when round tripping through
36+
// the dwarf encoding.
37+
for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) {
38+
int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false);
39+
EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false));
40+
}
41+
42+
// Verify that subregisters have no dwarf encoding.
43+
for (MCRegister LLSubReg :
44+
{AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) {
45+
EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);
3346
}
3447
}
3548
}
@@ -49,11 +62,24 @@ TEST(AMDGPU, TestWave32DwarfRegMapping) {
4962
// PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
5063
// S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
5164
// A0 => 2048, A255 => 2303
52-
for (int llvmReg :
65+
for (int DwarfEncoding :
5366
{16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
54-
MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
55-
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
56-
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true));
67+
MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);
68+
EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));
69+
EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));
70+
}
71+
72+
// We should get the correct LLVM register when round tripping through
73+
// the dwarf encoding.
74+
for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) {
75+
int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false);
76+
EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false));
77+
}
78+
79+
// Verify that subregisters have no dwarf encoding.
80+
for (MCRegister LLSubReg :
81+
{AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) {
82+
EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);
5783
}
5884
}
5985
}

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