Merge remote-tracking branch 'origin/main' into vpwideninductionrecipe

fhahn · fhahn · commit dcba17f35cd7 · 2024-12-15T20:48:05.000Z
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -1755,19 +1755,13 @@ void VPWidenIntOrFpInductionRecipe::execute(VPTransformState &State) {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 void VPWidenIntOrFpInductionRecipe::print(raw_ostream &O, const Twine &Indent,
                                           VPSlotTracker &SlotTracker) const {
-  O << Indent << "WIDEN-INDUCTION";
-  if (auto *TI = getTruncInst()) {
-    O << "\\l\"";
-    O << " +\n" << Indent << "\"  " << VPlanIngredient(getPHINode()) << "\\l\"";
-    O << " +\n" << Indent << "\"  " << VPlanIngredient(TI);
-  } else
-    O << " " << VPlanIngredient(getPHINode());
-
-  O << ", ";
-  getStepValue()->printAsOperand(O, SlotTracker);
+  O << Indent;
+  printAsOperand(O, SlotTracker);
+  O << " = WIDEN-INDUCTION  ";
+  printOperands(O, SlotTracker);
 
-  O << ", ";
-  getVFValue()->printAsOperand(O, SlotTracker);
+  if (auto *TI = getTruncInst())
+    O << " (truncated to " << *TI->getType() << ")";
 }
 #endif
 
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll b/llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
@@ -1,4 +1,4 @@
-; clang -target aarch64-eabi -O2 -march=armv8.5-a+memtag -fsanitize=memtag -S -emit-llvm test.cc
+; clang -target aarch64-eabi -O2 -fsanitize=memtag -S -emit-llvm test.cc
 ; void bar() {
 ;   throw 42;
 ; }
diff --git a/llvm/test/CodeGen/ARC/addrmode.ll b/llvm/test/CodeGen/ARC/addrmode.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arc < %s | FileCheck %s
+; RUN: llc -mtriple=arc < %s | FileCheck %s
 
 ; CHECK-LABEL: copy
 ; CHECK-NOT: add
diff --git a/llvm/test/CodeGen/ARC/alu.ll b/llvm/test/CodeGen/ARC/alu.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arc < %s | FileCheck %s
+; RUN: llc -mtriple=arc < %s | FileCheck %s
 
 ; CHECK-LABEL: add_r
 ; CHECK: add %r0, %r{{[01]}}, %r{{[01]}}
diff --git a/llvm/test/CodeGen/ARC/brcc.ll b/llvm/test/CodeGen/ARC/brcc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arc < %s | FileCheck %s
+; RUN: llc -mtriple=arc < %s | FileCheck %s
 
 ; CHECK-LABEL: brcc1:
 ; CHECK:         brne %r0, %r1, @.LBB0_2
diff --git a/llvm/test/CodeGen/ARC/call.ll b/llvm/test/CodeGen/ARC/call.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arc < %s | FileCheck %s
+; RUN: llc -mtriple=arc < %s | FileCheck %s
 
 
 declare i32 @goo1(i32) nounwind
diff --git a/llvm/test/CodeGen/ARC/intrinsics.ll b/llvm/test/CodeGen/ARC/intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arc < %s | FileCheck %s
+; RUN: llc -mtriple=arc < %s | FileCheck %s
 
 target triple = "arc"
 
diff --git a/llvm/test/CodeGen/ARC/ldst.ll b/llvm/test/CodeGen/ARC/ldst.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arc < %s | FileCheck %s
+; RUN: llc -mtriple=arc < %s | FileCheck %s
 
 ; CHECK-LABEL: load32
 ; CHECK: ld %r0, [%r0,16000]
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll b/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
 ; REQUIRES: asserts
 
 ; Check that the cost model makes vectorization non-profitable.
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll b/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
+; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
 ; Check that the loop has been interleaved.
 ; CHECK: store <64 x i32> %interleaved.vec
 
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll b/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
+; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
 ; Check that the loop is vectorized with VF=32.
 ; CHECK: wide.load{{.*}} = load <32 x i32>
 ; CHECK: wide.load{{.*}} = load <32 x i16>
diff --git a/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll b/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -O2 -S < %s
+; RUN: opt -O2 -S < %s
 ; REQUIRES: asserts
 ;
 ; -fvectorize-loops infinite compile/memory
diff --git a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll
@@ -1,4 +1,4 @@
-; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic
+; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -mcpu=hexagonv60 -relocation-model pic
 
 ; CHECK: jumpr
 
diff --git a/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll b/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
@@ -1,4 +1,4 @@
-; RUN: opt -Os -march=hexagon -S < %s | FileCheck %s
+; RUN: opt -Os -S < %s | FileCheck %s
 ; Don't reset the alignment on the struct to 1.
 ; CHECK: align 4
 
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
 ; CHECK-LABEL: define void @fred
 
 ; Check that this test does not crash.
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
 ;
 ; The number of nested selects caused the simplification loop to take
 ; more than the maximum number of iterations. This caused the compiler
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
@@ -2,8 +2,8 @@
 ; the Hexagon loop idiom recognition runs. This is to check that we still
 ; get this opportunity regardless of what happens before.
 
-; RUN: opt -O2 -march=hexagon -S < %s | FileCheck %s
-; RUN: opt -passes='default<O2>' -march=hexagon -S < %s | FileCheck %s
+; RUN: opt -O2 -S < %s | FileCheck %s
+; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
 
 target triple = "hexagon"
 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
 ; REQUIRES: asserts
 ;
 ; Check for sane output, this used to crash.
diff --git a/llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll b/llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-vc -S < %s | FileCheck %s
+; RUN: opt -hexagon-vc -S < %s | FileCheck %s
 
 ; Test that the HexagonVectorCombine pass identifies instruction
 ; pairs whose difference in pointers is zero. This creates a vector
diff --git a/llvm/test/CodeGen/Lanai/delay_filler.ll b/llvm/test/CodeGen/Lanai/delay_filler.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=lanai < %s | FileCheck %s
-; RUN: llc -march=lanai --lanai-nop-delay-filler < %s | \
+; RUN: llc < %s | FileCheck %s
+; RUN: llc --lanai-nop-delay-filler < %s | \
 ; RUN:   FileCheck %s --check-prefix=NOP
 
 ; CHECK: bt f
diff --git a/llvm/test/CodeGen/Lanai/lowering-128.ll b/llvm/test/CodeGen/Lanai/lowering-128.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=lanai < %s | FileCheck %s
+; RUN: llc < %s | FileCheck %s
 
 ; Tests that lowering wide registers (128 bits or more) works on Lanai.
 ; The emitted assembly is not checked, we just do a smoketest.
diff --git a/llvm/test/CodeGen/NVPTX/surf-read.ll b/llvm/test/CodeGen/NVPTX/surf-read.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
 
-target triple = "nvptx-unknown-nvcl"
+target triple = "nvptx64-unknown-nvcl"
 
 declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32)
 
diff --git a/llvm/test/CodeGen/NVPTX/surf-write.ll b/llvm/test/CodeGen/NVPTX/surf-write.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
 
 target triple = "nvptx-unknown-nvcl"
 
diff --git a/llvm/test/CodeGen/NVPTX/tex-read.ll b/llvm/test/CodeGen/NVPTX/tex-read.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
 
-target triple = "nvptx-unknown-nvcl"
+target triple = "nvptx64-unknown-nvcl"
 
 declare { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64, i64, i32)
 
diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
@@ -8,7 +8,7 @@
 ; Currently VSX support is disabled for this test because we generate lxsdx
 ; instead of lfd, and stxsdx instead of stfd.  That is a poor choice when we
 ; have reg+imm addressing, and is on the list of things to be fixed.
-; The second run step is to ensure that -march=ppc64le is adequate to select
+; The second run step is to ensure that is adequate to select
 ; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.
 
 target datalayout = "e-m:e-i64:64-n32:64"
diff --git a/llvm/test/CodeGen/Thumb2/bug-subw.ll b/llvm/test/CodeGen/Thumb2/bug-subw.ll
@@ -1,5 +1,5 @@
 ; pr23772 - [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80"
-; RUN: llc -march=thumb -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
+; RUN: llc -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
 ; CHECK-NOT: sub{{.*}} sp, r{{.*}}, #
 ; CHECK:     .fnend
 ; TODO: Missed optimization. The three instructions generated to subtract SP can be converged to a single one
diff --git a/llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll b/llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_60 | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_60 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_60 | %ptxas-verify %}
 target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
 target triple = "nvptx64-nvidia-cuda"
 
diff --git a/llvm/test/DebugInfo/X86/instr-ref-flag.ll b/llvm/test/DebugInfo/X86/instr-ref-flag.ll
@@ -1,10 +1,10 @@
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
 ; RUN: | FileCheck %s --check-prefixes=INSTRREFON
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
 ; RUN:    -experimental-debug-variable-locations=true \
 ; RUN: | FileCheck %s --check-prefixes=INSTRREFON
 
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
 ; RUN:    -experimental-debug-variable-locations=false \
 ; RUN: | FileCheck %s --check-prefixes=INSTRREFOFF \
 ; RUN:    --implicit-check-not=DBG_INSTR_REF
diff --git a/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll b/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
@@ -1,10 +1,10 @@
-; RUN: llc -O0  -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -O0 -dwarf-version=5 -debugger-tune=lldb -filetype=obj < %s \
 ; RUN:  | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -O0  -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -O0 -dwarf-version=5 -debugger-tune=gdb -filetype=obj < %s \
 ; RUN:  | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -force-instr-ref-livedebugvalues=1 -O0  -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=lldb -filetype=obj < %s \
 ; RUN:  | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -force-instr-ref-livedebugvalues=1 -O0  -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=gdb -filetype=obj < %s \
 ; RUN:  | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
 
 ; The call-site-params are created iff corresponding DISubprogram contains
diff --git a/llvm/test/DebugInfo/X86/single-dbg_value.ll b/llvm/test/DebugInfo/X86/single-dbg_value.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -stop-after=livedebugvalues -o - %s \
 ; RUN:   | FileCheck %s --check-prefix=SANITY
-; RUN: llc -march=x86-64 -o - %s -filetype=obj \
+; RUN: llc -o - %s -filetype=obj \
 ; RUN:   | llvm-dwarfdump -v -all - | FileCheck %s
 ;
 ; CHECK: .debug_info contents:
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=load-store-vectorizer -march=nvptx64 -mcpu=sm_35 -S < %s | FileCheck %s
+; RUN: opt -passes=load-store-vectorizer -mcpu=sm_35 -S < %s | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
 target triple = "nvptx64-nvidia-cuda"
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
@@ -23,7 +23,7 @@ define void @foo(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) {
 ; CHECK-NEXT: <x1> vector loop: {
 ; CHECK-NEXT:   vector.body:
 ; CHECK-NEXT:     EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_INC:%.*]]>
-; CHECK-NEXT:     WIDEN-INDUCTION %iv = phi 0, %iv.next, ir<1>, vp<[[VF]]>
+; CHECK-NEXT:     ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:     EMIT vp<[[CMP:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>
 ; CHECK-NEXT:   Successor(s): pred.store
 ; CHECK-EMPTY:
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
@@ -25,7 +25,7 @@ define void @sink_replicate_region_1(i32 %x, ptr %ptr, ptr noalias %dst) optsize
 ; CHECK-NEXT: vector.body:
 ; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
 ; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv>
-; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next, ir<1>, vp<[[VF]]>
+; CHECK-NEXT:   ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:   vp<[[STEPS:%.]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
 ; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>
 ; CHECK-NEXT: Successor(s): pred.load
@@ -135,7 +135,7 @@ define void @sink_replicate_region_2(i32 %x, i8 %y, ptr %ptr) optsize {
 ; CHECK-NEXT: vector.body:
 ; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
 ; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next>
-; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next, ir<1>, vp<[[VF]]>
+; CHECK-NEXT:   ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>
 ; CHECK-NEXT:   EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur>, ir<%recur.next>
 ; CHECK-NEXT:   Successor(s): pred.store
@@ -301,7 +301,7 @@ define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, ptr
 ; CHECK-NEXT: vector.body:
 ; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
 ; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv>
-; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next, ir<1>, vp<[[VF]]>
+; CHECK-NEXT:   ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:   vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
 ; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>
 ; CHECK-NEXT:   REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]>
@@ -419,7 +419,7 @@ define void @sink_replicate_region_after_replicate_region(ptr %ptr, ptr noalias
 ; CHECK-NEXT: vector.body:
 ; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
 ; CHECK-NEXT:   FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next>
-; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next, ir<1>, vp<[[VF]]>
+; CHECK-NEXT:   ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:   EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>
 ; CHECK-NEXT:   EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur>, ir<%recur.next>
 ; CHECK-NEXT: Successor(s): pred.store
diff --git a/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll b/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
@@ -52,7 +52,7 @@ for.end:
 ; CHECK-NEXT: <x1> vector loop: {
 ; CHECK-NEXT: vector.body:
 ; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
-; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi 0, %iv.next, ir<1>, vp<[[VF]]
+; CHECK-NEXT:   ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]
 ; CHECK-NEXT:   EMIT vp<[[COND:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>
 ; CHECK-NEXT:   WIDEN ir<%cond0> = icmp ult ir<%iv>, ir<13>
 ; CHECK-NEXT:   WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll b/llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
@@ -18,7 +18,7 @@ define void @iv_no_binary_op_in_descriptor(i1 %c, ptr %dst) {
 ; CHECK-NEXT: <x1> vector loop: {
 ; CHECK-NEXT:   vector.body:
 ; CHECK-NEXT:     EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
-; CHECK-NEXT:     WIDEN-INDUCTION %iv = phi 0, %iv.next.p, ir<1>, vp<[[VF]]>
+; CHECK-NEXT:     ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:     vp<[[STEPS:%.+]]>    = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
 ; CHECK-NEXT:     CLONE ir<%gep> = getelementptr inbounds ir<%dst>, vp<[[STEPS:%.+]]>
 ; CHECK-NEXT:     vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%gep>
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
@@ -89,7 +89,7 @@ define void @print_widen_gep_and_select(i64 %n, ptr noalias %y, ptr noalias %x,
 ; CHECK-NEXT: <x1> vector loop: {
 ; CHECK-NEXT: vector.body:
 ; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
-; CHECK-NEXT:   WIDEN-INDUCTION %iv = phi %iv.next, 0, ir<1>, vp<[[VF]]
+; CHECK-NEXT:   ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:   vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
 ; CHECK-NEXT:   WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr inbounds ir<%y>, ir<%iv>
 ; CHECK-NEXT:   vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%arrayidx>
@@ -295,7 +295,7 @@ define void @print_replicate_predicated_phi(i64 %n, ptr %x) {
 ; CHECK-NEXT: <x1> vector loop: {
 ; CHECK-NEXT: vector.body:
 ; CHECK-NEXT:   EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
-; CHECK-NEXT:   WIDEN-INDUCTION %i = phi 0, %i.next, ir<1>, vp<[[VF]]>
+; CHECK-NEXT:   ir<%i> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:   vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
 ; CHECK-NEXT:   WIDEN ir<%cmp> = icmp ult ir<%i>, ir<5>
 ; CHECK-NEXT: Successor(s): pred.udiv
@@ -652,10 +652,8 @@ define void @print_expand_scev(i64 %y, ptr %ptr) {
 ; CHECK-EMPTY:
 ; CHECK-NEXT: <x1> vector loop: {
 ; CHECK-NEXT:   vector.body:
-; CHECK-NEXT:    EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
-; CHECK-NEXT:     WIDEN-INDUCTION\l" +
-; CHECK-NEXT:     "  %iv = phi %iv.next, 0\l" +
-; CHECK-NEXT:     "  %v2 = trunc %iv, vp<[[EXP_SCEV]]>, vp<[[VF]]>
+; CHECK-NEXT:     EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
+; CHECK-NEXT:     ir<%iv> = WIDEN-INDUCTION ir<0>, vp<[[EXP_SCEV]]>, vp<[[VF]]> (truncated to i8)
 ; CHECK-NEXT:     vp<[[DERIVED_IV:%.+]]> = DERIVED-IV ir<0> + vp<[[CAN_IV]]> * vp<[[EXP_SCEV]]>
 ; CHECK-NEXT:     vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DERIVED_IV]]>, vp<[[EXP_SCEV]]>
 ; CHECK-NEXT:     WIDEN ir<%v3> = add nuw ir<%iv>, ir<1>
@@ -721,7 +719,7 @@ define i32 @print_exit_value(ptr %ptr, i32 %off) {
 ; CHECK-NEXT: <x1> vector loop: {
 ; CHECK-NEXT:   vector.body:
 ; CHECK-NEXT:    EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
-; CHECK-NEXT:     WIDEN-INDUCTION %iv = phi 0, %iv.next, ir<1>, vp<[[VF]]>
+; CHECK-NEXT:     ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
 ; CHECK-NEXT:     vp<[[STEPS:%.+]]>    = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
 ; CHECK-NEXT:     CLONE ir<%gep> = getelementptr inbounds ir<%ptr>, vp<[[STEPS]]>
 ; CHECK-NEXT:     WIDEN ir<%add> = add ir<%iv>, ir<%off>
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; clang -target aarch64-eabi -O2 -march=armv8.5-a+memtag -fsanitize=memtag -S -emit-llvm test.cc`
	`1`	`+; clang -target aarch64-eabi -O2 -fsanitize=memtag -S -emit-llvm test.cc`
`2`	`2`	`; void bar() {`
`3`	`3`	`; throw 42;`
`4`	`4`	`; }`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: llc -march=arc < %s \| FileCheck %s`
	`1`	`+; RUN: llc -mtriple=arc < %s \| FileCheck %s`
`2`	`2`
`3`	`3`	`; CHECK-LABEL: copy`
`4`	`4`	`; CHECK-NOT: add`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: opt -march=hexagon -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 \| FileCheck %s`
	`1`	`+; RUN: opt -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 \| FileCheck %s`
`2`	`2`	`; REQUIRES: asserts`
`3`	`3`
`4`	`4`	`; Check that the cost model makes vectorization non-profitable.`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s \| FileCheck %s`
	`1`	`+; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s \| FileCheck %s`
`2`	`2`	`; Check that the loop has been interleaved.`
`3`	`3`	`; CHECK: store <64 x i32> %interleaved.vec`
`4`	`4`