Skip to content

Commit dcbb655

Browse files
topperctopperc
committed
fixup! rename vecpolicy -> vec_policy.
1 parent b5303f6 commit dcbb655

File tree

4 files changed

+43
-43
lines changed

4 files changed

+43
-43
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -336,7 +336,7 @@ enum OperandType : unsigned {
336336
// Operand is a 3-bit rounding mode where only RTZ is valid.
337337
OPERAND_RTZARG,
338338
// Vector policy operand.
339-
OPERAND_VECPOLICY,
339+
OPERAND_VEC_POLICY,
340340
// Vector SEW operand.
341341
OPERAND_SEW,
342342
OPERAND_LAST_RISCV_IMM = OPERAND_SEW,

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2542,7 +2542,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
25422542
case RISCVOp::OPERAND_RTZARG:
25432543
Ok = Imm == RISCVFPRndMode::RTZ;
25442544
break;
2545-
case RISCVOp::OPERAND_VECPOLICY:
2545+
case RISCVOp::OPERAND_VEC_POLICY:
25462546
Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm;
25472547
break;
25482548
case RISCVOp::OPERAND_SEW:

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 39 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -84,8 +84,8 @@ def AVL : RegisterOperand<GPRNoX0> {
8484
let OperandType = "OPERAND_AVL";
8585
}
8686

87-
def vecpolicy : RISCVOp {
88-
let OperandType = "OPERAND_VECPOLICY";
87+
def vec_policy : RISCVOp {
88+
let OperandType = "OPERAND_VEC_POLICY";
8989
}
9090

9191
def sew : RISCVOp {
@@ -773,7 +773,7 @@ class VPseudoUSLoadNoMask<VReg RetClass,
773773
int EEW> :
774774
Pseudo<(outs RetClass:$rd),
775775
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sew:$sew,
776-
vecpolicy:$policy), []>,
776+
vec_policy:$policy), []>,
777777
RISCVVPseudo,
778778
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
779779
let mayLoad = 1;
@@ -790,7 +790,7 @@ class VPseudoUSLoadMask<VReg RetClass,
790790
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
791791
(ins GetVRegNoV0<RetClass>.R:$passthru,
792792
GPRMem:$rs1,
793-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
793+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
794794
RISCVVPseudo,
795795
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
796796
let mayLoad = 1;
@@ -807,7 +807,7 @@ class VPseudoUSLoadFFNoMask<VReg RetClass,
807807
int EEW> :
808808
Pseudo<(outs RetClass:$rd, GPR:$vl),
809809
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
810-
sew:$sew, vecpolicy:$policy), []>,
810+
sew:$sew, vec_policy:$policy), []>,
811811
RISCVVPseudo,
812812
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
813813
let mayLoad = 1;
@@ -824,7 +824,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
824824
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
825825
(ins GetVRegNoV0<RetClass>.R:$passthru,
826826
GPRMem:$rs1,
827-
VMaskOp:$vm, AVL:$avl, sew:$sew, vecpolicy:$policy), []>,
827+
VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
828828
RISCVVPseudo,
829829
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
830830
let mayLoad = 1;
@@ -841,7 +841,7 @@ class VPseudoSLoadNoMask<VReg RetClass,
841841
int EEW> :
842842
Pseudo<(outs RetClass:$rd),
843843
(ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
844-
sew:$sew, vecpolicy:$policy), []>,
844+
sew:$sew, vec_policy:$policy), []>,
845845
RISCVVPseudo,
846846
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
847847
let mayLoad = 1;
@@ -858,7 +858,7 @@ class VPseudoSLoadMask<VReg RetClass,
858858
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
859859
(ins GetVRegNoV0<RetClass>.R:$passthru,
860860
GPRMem:$rs1, GPR:$rs2,
861-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
861+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
862862
RISCVVPseudo,
863863
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
864864
let mayLoad = 1;
@@ -880,7 +880,7 @@ class VPseudoILoadNoMask<VReg RetClass,
880880
int TargetConstraintType = 1> :
881881
Pseudo<(outs RetClass:$rd),
882882
(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
883-
sew:$sew, vecpolicy:$policy), []>,
883+
sew:$sew, vec_policy:$policy), []>,
884884
RISCVVPseudo,
885885
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
886886
let mayLoad = 1;
@@ -903,7 +903,7 @@ class VPseudoILoadMask<VReg RetClass,
903903
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
904904
(ins GetVRegNoV0<RetClass>.R:$passthru,
905905
GPRMem:$rs1, IdxClass:$rs2,
906-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
906+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
907907
RISCVVPseudo,
908908
RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
909909
let mayLoad = 1;
@@ -975,7 +975,7 @@ class VPseudoSStoreMask<VReg StClass,
975975
class VPseudoNullaryNoMask<VReg RegClass> :
976976
Pseudo<(outs RegClass:$rd),
977977
(ins RegClass:$passthru,
978-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
978+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
979979
RISCVVPseudo {
980980
let mayLoad = 0;
981981
let mayStore = 0;
@@ -989,7 +989,7 @@ class VPseudoNullaryNoMask<VReg RegClass> :
989989
class VPseudoNullaryMask<VReg RegClass> :
990990
Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
991991
(ins GetVRegNoV0<RegClass>.R:$passthru,
992-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
992+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
993993
RISCVVPseudo {
994994
let mayLoad = 0;
995995
let mayStore = 0;
@@ -1024,7 +1024,7 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
10241024
int TargetConstraintType = 1> :
10251025
Pseudo<(outs RetClass:$rd),
10261026
(ins RetClass:$passthru, OpClass:$rs2,
1027-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1027+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
10281028
RISCVVPseudo {
10291029
let mayLoad = 0;
10301030
let mayStore = 0;
@@ -1058,7 +1058,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
10581058
int TargetConstraintType = 1> :
10591059
Pseudo<(outs RetClass:$rd),
10601060
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm,
1061-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1061+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
10621062
RISCVVPseudo {
10631063
let mayLoad = 0;
10641064
let mayStore = 0;
@@ -1078,7 +1078,7 @@ class VPseudoUnaryMask<VReg RetClass,
10781078
int TargetConstraintType = 1> :
10791079
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
10801080
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
1081-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1081+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
10821082
RISCVVPseudo {
10831083
let mayLoad = 0;
10841084
let mayStore = 0;
@@ -1098,7 +1098,7 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
10981098
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
10991099
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
11001100
VMaskOp:$vm, ixlenimm:$rm,
1101-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1101+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
11021102
RISCVVPseudo {
11031103
let mayLoad = 0;
11041104
let mayStore = 0;
@@ -1118,7 +1118,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
11181118
string Constraint = ""> :
11191119
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
11201120
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
1121-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []> {
1121+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {
11221122
let mayLoad = 0;
11231123
let mayStore = 0;
11241124
let hasSideEffects = 0;
@@ -1136,7 +1136,7 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
11361136
int TargetConstraintType = 1> :
11371137
Pseudo<(outs RetClass:$rd),
11381138
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
1139-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1139+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
11401140
RISCVVPseudo {
11411141
let mayLoad = 0;
11421142
let mayStore = 0;
@@ -1156,7 +1156,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
11561156
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
11571157
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
11581158
VMaskOp:$vm, ixlenimm:$frm,
1159-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1159+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
11601160
RISCVVPseudo {
11611161
let mayLoad = 0;
11621162
let mayStore = 0;
@@ -1231,7 +1231,7 @@ class VPseudoBinaryNoMaskPolicy<VReg RetClass,
12311231
int TargetConstraintType = 1> :
12321232
Pseudo<(outs RetClass:$rd),
12331233
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
1234-
sew:$sew, vecpolicy:$policy), []>,
1234+
sew:$sew, vec_policy:$policy), []>,
12351235
RISCVVPseudo {
12361236
let mayLoad = 0;
12371237
let mayStore = 0;
@@ -1251,7 +1251,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
12511251
int TargetConstraintType = 1> :
12521252
Pseudo<(outs RetClass:$rd),
12531253
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
1254-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1254+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
12551255
RISCVVPseudo {
12561256
let mayLoad = 0;
12571257
let mayStore = 0;
@@ -1274,7 +1274,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
12741274
(ins GetVRegNoV0<RetClass>.R:$passthru,
12751275
Op1Class:$rs2, Op2Class:$rs1,
12761276
VMaskOp:$vm, ixlenimm:$rm, AVL:$vl,
1277-
sew:$sew, vecpolicy:$policy), []>,
1277+
sew:$sew, vec_policy:$policy), []>,
12781278
RISCVVPseudo {
12791279
let mayLoad = 0;
12801280
let mayStore = 0;
@@ -1297,7 +1297,7 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
12971297
int TargetConstraintType = 1> :
12981298
Pseudo<(outs RetClass:$rd),
12991299
(ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew,
1300-
vecpolicy:$policy), []>,
1300+
vec_policy:$policy), []>,
13011301
RISCVVPseudo {
13021302
let mayLoad = 0;
13031303
let mayStore = 0;
@@ -1319,7 +1319,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
13191319
(ins RetClass:$rs2, Op2Class:$rs1,
13201320
ixlenimm:$rm,
13211321
AVL:$vl, sew:$sew,
1322-
vecpolicy:$policy), []>,
1322+
vec_policy:$policy), []>,
13231323
RISCVVPseudo {
13241324
let mayLoad = 0;
13251325
let mayStore = 0;
@@ -1371,7 +1371,7 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
13711371
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
13721372
(ins GetVRegNoV0<RetClass>.R:$passthru,
13731373
Op1Class:$rs2, Op2Class:$rs1,
1374-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1374+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
13751375
RISCVVPseudo {
13761376
let mayLoad = 0;
13771377
let mayStore = 0;
@@ -1390,7 +1390,7 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
13901390
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
13911391
(ins GetVRegNoV0<RetClass>.R:$passthru,
13921392
Op1Class:$rs2, Op2Class:$rs1,
1393-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1393+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
13941394
RISCVVPseudo {
13951395
let mayLoad = 0;
13961396
let mayStore = 0;
@@ -1409,7 +1409,7 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
14091409
Op1Class:$rs2, Op2Class:$rs1,
14101410
VMaskOp:$vm,
14111411
ixlenimm:$rm,
1412-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1412+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
14131413
RISCVVPseudo {
14141414
let mayLoad = 0;
14151415
let mayStore = 0;
@@ -1453,7 +1453,7 @@ class VPseudoTiedBinaryMask<VReg RetClass,
14531453
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
14541454
(ins GetVRegNoV0<RetClass>.R:$passthru,
14551455
Op2Class:$rs1,
1456-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1456+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
14571457
RISCVVPseudo {
14581458
let mayLoad = 0;
14591459
let mayStore = 0;
@@ -1476,7 +1476,7 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
14761476
Op2Class:$rs1,
14771477
VMaskOp:$vm,
14781478
ixlenimm:$rm,
1479-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1479+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
14801480
RISCVVPseudo {
14811481
let mayLoad = 0;
14821482
let mayStore = 0;
@@ -1559,7 +1559,7 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
15591559
int TargetConstraintType = 1> :
15601560
Pseudo<(outs RetClass:$rd),
15611561
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
1562-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1562+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
15631563
RISCVVPseudo {
15641564
let mayLoad = 0;
15651565
let mayStore = 0;
@@ -1578,7 +1578,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
15781578
int TargetConstraintType = 1> :
15791579
Pseudo<(outs RetClass:$rd),
15801580
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
1581-
ixlenimm:$rm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1581+
ixlenimm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
15821582
RISCVVPseudo {
15831583
let mayLoad = 0;
15841584
let mayStore = 0;
@@ -1597,7 +1597,7 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
15971597
bits<4> NF> :
15981598
Pseudo<(outs RetClass:$rd),
15991599
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
1600-
sew:$sew, vecpolicy:$policy), []>,
1600+
sew:$sew, vec_policy:$policy), []>,
16011601
RISCVVPseudo,
16021602
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
16031603
let mayLoad = 1;
@@ -1614,7 +1614,7 @@ class VPseudoUSSegLoadMask<VReg RetClass,
16141614
bits<4> NF> :
16151615
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
16161616
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
1617-
VMaskOp:$vm, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
1617+
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
16181618
RISCVVPseudo,
16191619
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
16201620
let mayLoad = 1;
@@ -1632,7 +1632,7 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
16321632
bits<4> NF> :
16331633
Pseudo<(outs RetClass:$rd, GPR:$vl),
16341634
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
1635-
sew:$sew, vecpolicy:$policy), []>,
1635+
sew:$sew, vec_policy:$policy), []>,
16361636
RISCVVPseudo,
16371637
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
16381638
let mayLoad = 1;
@@ -1649,7 +1649,7 @@ class VPseudoUSSegLoadFFMask<VReg RetClass,
16491649
bits<4> NF> :
16501650
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
16511651
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
1652-
VMaskOp:$vm, AVL:$avl, sew:$sew, vecpolicy:$policy), []>,
1652+
VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
16531653
RISCVVPseudo,
16541654
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
16551655
let mayLoad = 1;
@@ -1667,7 +1667,7 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
16671667
bits<4> NF> :
16681668
Pseudo<(outs RetClass:$rd),
16691669
(ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl,
1670-
sew:$sew, vecpolicy:$policy), []>,
1670+
sew:$sew, vec_policy:$policy), []>,
16711671
RISCVVPseudo,
16721672
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
16731673
let mayLoad = 1;
@@ -1685,7 +1685,7 @@ class VPseudoSSegLoadMask<VReg RetClass,
16851685
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
16861686
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
16871687
GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
1688-
vecpolicy:$policy), []>,
1688+
vec_policy:$policy), []>,
16891689
RISCVVPseudo,
16901690
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
16911691
let mayLoad = 1;
@@ -1706,7 +1706,7 @@ class VPseudoISegLoadNoMask<VReg RetClass,
17061706
bit Ordered> :
17071707
Pseudo<(outs RetClass:$rd),
17081708
(ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl,
1709-
sew:$sew, vecpolicy:$policy), []>,
1709+
sew:$sew, vec_policy:$policy), []>,
17101710
RISCVVPseudo,
17111711
RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
17121712
let mayLoad = 1;
@@ -1729,7 +1729,7 @@ class VPseudoISegLoadMask<VReg RetClass,
17291729
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
17301730
(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
17311731
IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
1732-
vecpolicy:$policy), []>,
1732+
vec_policy:$policy), []>,
17331733
RISCVVPseudo,
17341734
RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
17351735
let mayLoad = 1;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ class ZvkMxSet<string vd_lmul> {
231231

232232
class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
233233
Pseudo<(outs RetClass:$rd_wb),
234-
(ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
234+
(ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
235235
RISCVVPseudo {
236236
let mayLoad = 0;
237237
let mayStore = 0;
@@ -248,7 +248,7 @@ class VPseudoTernaryNoMask_Zvk<VReg RetClass,
248248
DAGOperand Op2Class> :
249249
Pseudo<(outs RetClass:$rd_wb),
250250
(ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
251-
AVL:$vl, sew:$sew, vecpolicy:$policy), []>,
251+
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
252252
RISCVVPseudo {
253253
let mayLoad = 0;
254254
let mayStore = 0;

0 commit comments

Comments
 (0)