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[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)
This matches the underlying function in MachineMemOperand and how it is printed when BaseAlign differs from Align.
1 parent 7f4a910 commit dcd62f3

14 files changed

+199
-229
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1386,7 +1386,7 @@ class MemSDNode : public SDNode {
13861386
bool writeMem() const { return MMO->isStore(); }
13871387

13881388
/// Returns alignment and volatility of the memory access
1389-
Align getOriginalAlign() const { return MMO->getBaseAlign(); }
1389+
Align getBaseAlign() const { return MMO->getBaseAlign(); }
13901390
Align getAlign() const { return MMO->getAlign(); }
13911391

13921392
/// Return the SubclassData value, without HasDebugValue. This contains an

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 19 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -12393,8 +12393,8 @@ SDValue DAGCombiner::visitMSTORE(SDNode *N) {
1239312393
!MST->isCompressingStore() && !MST->isTruncatingStore())
1239412394
return DAG.getStore(MST->getChain(), SDLoc(N), MST->getValue(),
1239512395
MST->getBasePtr(), MST->getPointerInfo(),
12396-
MST->getOriginalAlign(),
12397-
MST->getMemOperand()->getFlags(), MST->getAAInfo());
12396+
MST->getBaseAlign(), MST->getMemOperand()->getFlags(),
12397+
MST->getAAInfo());
1239812398

1239912399
// Try transforming N to an indexed store.
1240012400
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
@@ -12578,7 +12578,7 @@ SDValue DAGCombiner::visitMLOAD(SDNode *N) {
1257812578
!MLD->isExpandingLoad() && MLD->getExtensionType() == ISD::NON_EXTLOAD) {
1257912579
SDValue NewLd = DAG.getLoad(
1258012580
N->getValueType(0), SDLoc(N), MLD->getChain(), MLD->getBasePtr(),
12581-
MLD->getPointerInfo(), MLD->getOriginalAlign(),
12581+
MLD->getPointerInfo(), MLD->getBaseAlign(),
1258212582
MLD->getMemOperand()->getFlags(), MLD->getAAInfo(), MLD->getRanges());
1258312583
return CombineTo(N, NewLd, NewLd.getValue(1));
1258412584
}
@@ -13618,7 +13618,7 @@ SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
1361813618
SDValue SplitLoad =
1361913619
DAG.getExtLoad(ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(),
1362013620
BasePtr, LN0->getPointerInfo().getWithOffset(Offset),
13621-
SplitSrcVT, LN0->getOriginalAlign(),
13621+
SplitSrcVT, LN0->getBaseAlign(),
1362213622
LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
1362313623

1362413624
BasePtr = DAG.getMemBasePlusOffset(BasePtr, TypeSize::getFixed(Stride), DL);
@@ -15175,15 +15175,15 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
1517515175
} else if (CR.getBitWidth() == BitSize)
1517615176
NewRanges = OldRanges;
1517715177
}
15178-
Load = DAG.getLoad(
15179-
VT, DL, LN0->getChain(), NewPtr,
15180-
LN0->getPointerInfo().getWithOffset(PtrOff), LN0->getOriginalAlign(),
15181-
LN0->getMemOperand()->getFlags(), LN0->getAAInfo(), NewRanges);
15178+
Load = DAG.getLoad(VT, DL, LN0->getChain(), NewPtr,
15179+
LN0->getPointerInfo().getWithOffset(PtrOff),
15180+
LN0->getBaseAlign(), LN0->getMemOperand()->getFlags(),
15181+
LN0->getAAInfo(), NewRanges);
1518215182
} else
1518315183
Load = DAG.getExtLoad(ExtType, DL, VT, LN0->getChain(), NewPtr,
1518415184
LN0->getPointerInfo().getWithOffset(PtrOff), ExtVT,
15185-
LN0->getOriginalAlign(),
15186-
LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
15185+
LN0->getBaseAlign(), LN0->getMemOperand()->getFlags(),
15186+
LN0->getAAInfo());
1518715187

1518815188
// Replace the old load's chain with the new load's chain.
1518915189
WorklistRemover DeadNodes(*this);
@@ -20599,16 +20599,15 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
2059920599
++OpsNarrowed;
2060020600
if (UseTruncStore)
2060120601
return DAG.getTruncStore(St->getChain(), SDLoc(St), IVal, Ptr,
20602-
St->getPointerInfo().getWithOffset(StOffset),
20603-
VT, St->getOriginalAlign());
20602+
St->getPointerInfo().getWithOffset(StOffset), VT,
20603+
St->getBaseAlign());
2060420604

2060520605
// Truncate down to the new size.
2060620606
IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
2060720607

20608-
return DAG
20609-
.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
20610-
St->getPointerInfo().getWithOffset(StOffset),
20611-
St->getOriginalAlign());
20608+
return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
20609+
St->getPointerInfo().getWithOffset(StOffset),
20610+
St->getBaseAlign());
2061220611
}
2061320612

2061420613
/// Look for sequence of load / op / store where op is one of 'or', 'xor', and
@@ -22129,11 +22128,11 @@ SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
2212922128
AAMDNodes AAInfo = ST->getAAInfo();
2213022129

2213122130
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
22132-
ST->getOriginalAlign(), MMOFlags, AAInfo);
22131+
ST->getBaseAlign(), MMOFlags, AAInfo);
2213322132
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(4), DL);
2213422133
SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr,
2213522134
ST->getPointerInfo().getWithOffset(4),
22136-
ST->getOriginalAlign(), MMOFlags, AAInfo);
22135+
ST->getBaseAlign(), MMOFlags, AAInfo);
2213722136
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2213822137
St0, St1);
2213922138
}
@@ -22604,13 +22603,13 @@ SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
2260422603
SDValue Ptr = ST->getBasePtr();
2260522604
// Lower value store.
2260622605
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
22607-
ST->getOriginalAlign(), MMOFlags, AAInfo);
22606+
ST->getBaseAlign(), MMOFlags, AAInfo);
2260822607
Ptr =
2260922608
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(HalfValBitSize / 8), DL);
2261022609
// Higher value store.
2261122610
SDValue St1 = DAG.getStore(
2261222611
St0, DL, Hi, Ptr, ST->getPointerInfo().getWithOffset(HalfValBitSize / 8),
22613-
ST->getOriginalAlign(), MMOFlags, AAInfo);
22612+
ST->getBaseAlign(), MMOFlags, AAInfo);
2261422613
return St1;
2261522614
}
2261622615

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 18 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -441,7 +441,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
441441
bitcastToAPInt().zextOrTrunc(32),
442442
SDLoc(CFP), MVT::i32);
443443
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
444-
ST->getOriginalAlign(), MMOFlags, AAInfo);
444+
ST->getBaseAlign(), MMOFlags, AAInfo);
445445
}
446446

447447
if (CFP->getValueType(0) == MVT::f64 &&
@@ -451,7 +451,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
451451
SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
452452
zextOrTrunc(64), SDLoc(CFP), MVT::i64);
453453
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
454-
ST->getOriginalAlign(), MMOFlags, AAInfo);
454+
ST->getBaseAlign(), MMOFlags, AAInfo);
455455
}
456456

457457
if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
@@ -465,11 +465,11 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
465465
std::swap(Lo, Hi);
466466

467467
Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(),
468-
ST->getOriginalAlign(), MMOFlags, AAInfo);
468+
ST->getBaseAlign(), MMOFlags, AAInfo);
469469
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(4), dl);
470470
Hi = DAG.getStore(Chain, dl, Hi, Ptr,
471471
ST->getPointerInfo().getWithOffset(4),
472-
ST->getOriginalAlign(), MMOFlags, AAInfo);
472+
ST->getBaseAlign(), MMOFlags, AAInfo);
473473

474474
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
475475
}
@@ -525,7 +525,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
525525
"Can only promote stores to same size type");
526526
Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
527527
SDValue Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
528-
ST->getOriginalAlign(), MMOFlags, AAInfo);
528+
ST->getBaseAlign(), MMOFlags, AAInfo);
529529
ReplaceNode(SDValue(Node, 0), Result);
530530
break;
531531
}
@@ -548,7 +548,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
548548
Value = DAG.getZeroExtendInReg(Value, dl, StVT);
549549
SDValue Result =
550550
DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
551-
ST->getOriginalAlign(), MMOFlags, AAInfo);
551+
ST->getBaseAlign(), MMOFlags, AAInfo);
552552
ReplaceNode(SDValue(Node, 0), Result);
553553
} else if (!StVT.isVector() && !isPowerOf2_64(StWidth.getFixedValue())) {
554554
// If not storing a power-of-2 number of bits, expand as two stores.
@@ -571,7 +571,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
571571
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
572572
// Store the bottom RoundWidth bits.
573573
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
574-
RoundVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
574+
RoundVT, ST->getBaseAlign(), MMOFlags, AAInfo);
575575

576576
// Store the remaining ExtraWidth bits.
577577
IncrementSize = RoundWidth / 8;
@@ -583,7 +583,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
583583
TLI.getShiftAmountTy(Value.getValueType(), DL)));
584584
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
585585
ST->getPointerInfo().getWithOffset(IncrementSize),
586-
ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
586+
ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
587587
} else {
588588
// Big endian - avoid unaligned stores.
589589
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
@@ -593,7 +593,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
593593
DAG.getConstant(ExtraWidth, dl,
594594
TLI.getShiftAmountTy(Value.getValueType(), DL)));
595595
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), RoundVT,
596-
ST->getOriginalAlign(), MMOFlags, AAInfo);
596+
ST->getBaseAlign(), MMOFlags, AAInfo);
597597

598598
// Store the remaining ExtraWidth bits.
599599
IncrementSize = RoundWidth / 8;
@@ -602,7 +602,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
602602
Ptr.getValueType()));
603603
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
604604
ST->getPointerInfo().getWithOffset(IncrementSize),
605-
ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
605+
ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
606606
}
607607

608608
// The order of the stores doesn't matter.
@@ -638,16 +638,15 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
638638
if (TLI.isTypeLegal(StVT)) {
639639
Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
640640
Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
641-
ST->getOriginalAlign(), MMOFlags, AAInfo);
641+
ST->getBaseAlign(), MMOFlags, AAInfo);
642642
} else {
643643
// The in-memory type isn't legal. Truncate to the type it would promote
644644
// to, and then do a truncstore.
645645
Value = DAG.getNode(ISD::TRUNCATE, dl,
646646
TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
647647
Value);
648-
Result =
649-
DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), StVT,
650-
ST->getOriginalAlign(), MMOFlags, AAInfo);
648+
Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
649+
StVT, ST->getBaseAlign(), MMOFlags, AAInfo);
651650
}
652651

653652
ReplaceNode(SDValue(Node, 0), Result);
@@ -753,7 +752,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
753752

754753
SDValue Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
755754
Chain, Ptr, LD->getPointerInfo(), NVT,
756-
LD->getOriginalAlign(), MMOFlags, AAInfo);
755+
LD->getBaseAlign(), MMOFlags, AAInfo);
757756

758757
Ch = Result.getValue(1); // The chain.
759758

@@ -792,7 +791,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
792791
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
793792
// Load the bottom RoundWidth bits.
794793
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
795-
LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
794+
LD->getPointerInfo(), RoundVT, LD->getBaseAlign(),
796795
MMOFlags, AAInfo);
797796

798797
// Load the remaining ExtraWidth bits.
@@ -801,7 +800,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
801800
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
802801
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
803802
LD->getPointerInfo().getWithOffset(IncrementSize),
804-
ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
803+
ExtraVT, LD->getBaseAlign(), MMOFlags, AAInfo);
805804

806805
// Build a factor node to remember that this load is independent of
807806
// the other one.
@@ -821,7 +820,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
821820
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
822821
// Load the top RoundWidth bits.
823822
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
824-
LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
823+
LD->getPointerInfo(), RoundVT, LD->getBaseAlign(),
825824
MMOFlags, AAInfo);
826825

827826
// Load the remaining ExtraWidth bits.
@@ -830,7 +829,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
830829
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
831830
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
832831
LD->getPointerInfo().getWithOffset(IncrementSize),
833-
ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
832+
ExtraVT, LD->getBaseAlign(), MMOFlags, AAInfo);
834833

835834
// Build a factor node to remember that this load is independent of
836835
// the other one.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -968,8 +968,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
968968
if (L->getExtensionType() == ISD::NON_EXTLOAD) {
969969
NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
970970
L->getChain(), L->getBasePtr(), L->getOffset(),
971-
L->getPointerInfo(), NVT, L->getOriginalAlign(),
972-
MMOFlags, L->getAAInfo());
971+
L->getPointerInfo(), NVT, L->getBaseAlign(), MMOFlags,
972+
L->getAAInfo());
973973
// Legalized the chain result - switch anything that used the old chain to
974974
// use the new one.
975975
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
@@ -979,8 +979,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
979979
// Do a non-extending load followed by FP_EXTEND.
980980
NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
981981
dl, L->getChain(), L->getBasePtr(), L->getOffset(),
982-
L->getPointerInfo(), L->getMemoryVT(),
983-
L->getOriginalAlign(), MMOFlags, L->getAAInfo());
982+
L->getPointerInfo(), L->getMemoryVT(), L->getBaseAlign(),
983+
MMOFlags, L->getAAInfo());
984984
// Legalized the chain result - switch anything that used the old chain to
985985
// use the new one.
986986
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
@@ -3122,7 +3122,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {
31223122
SDValue newL = DAG.getLoad(
31233123
L->getAddressingMode(), L->getExtensionType(), IVT, SDLoc(N),
31243124
L->getChain(), L->getBasePtr(), L->getOffset(), L->getPointerInfo(), IVT,
3125-
L->getOriginalAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
3125+
L->getBaseAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
31263126
// Legalize the chain result by replacing uses of the old value chain with the
31273127
// new one
31283128
ReplaceValueWith(SDValue(N, 1), newL.getValue(1));
@@ -3551,7 +3551,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_LOAD(SDNode *N) {
35513551
SDValue NewL =
35523552
DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), MVT::i16,
35533553
SDLoc(N), L->getChain(), L->getBasePtr(), L->getOffset(),
3554-
L->getPointerInfo(), MVT::i16, L->getOriginalAlign(),
3554+
L->getPointerInfo(), MVT::i16, L->getBaseAlign(),
35553555
L->getMemOperand()->getFlags(), L->getAAInfo());
35563556
// Legalize the chain result by replacing uses of the old value chain with the
35573557
// new one

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