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Extend patch to all arm builtins that have the same pattern
1 parent b60c65d commit dd31999

19 files changed

+51
-43
lines changed

‎compiler-rt/lib/builtins/arm/adddf3vfp.S‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,10 @@ DEFINE_COMPILERRT_FUNCTION(__adddf3vfp)
1919
#if defined(COMPILER_RT_ARMHF_TARGET)
2020
vadd.f64 d0, d0, d1
2121
#else
22-
vmov d6, r0, r1 // move first param from r0/r1 pair into d6
23-
vmov d7, r2, r3 // move second param from r2/r3 pair into d7
22+
VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
23+
VMOV_TO_DOUBLE(d7, r2, r3) // move second param from r2/r3 pair into d7
2424
vadd.f64 d6, d6, d7
25-
vmov r0, r1, d6 // move result back to r0/r1 pair
25+
VMOV_FROM_DOUBLE(r0, r1, d6) // move result back to r0/r1 pair
2626
#endif
2727
bx lr
2828
END_COMPILERRT_FUNCTION(__adddf3vfp)

‎compiler-rt/lib/builtins/arm/aeabi_dcmp.S‎

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
77
//===----------------------------------------------------------------------===//
88

99
#include "../assembly.h"
10-
#include "../int_endianness.h"
1110

1211
// int __aeabi_dcmp{eq,lt,le,ge,gt}(double a, double b) {
1312
// int result = __{eq,lt,le,ge,gt}df2(a, b);
@@ -18,17 +17,10 @@
1817
// }
1918
// }
2019

21-
2220
#if defined(COMPILER_RT_ARMHF_TARGET)
23-
# if _YUGA_BIG_ENDIAN
24-
# define CONVERT_DCMP_ARGS_TO_DF2_ARGS \
25-
vmov d0, r1, r0 SEPARATOR \
26-
vmov d1, r3, r2
27-
# else
28-
# define CONVERT_DCMP_ARGS_TO_DF2_ARGS \
29-
vmov d0, r0, r1 SEPARATOR \
30-
vmov d1, r2, r3
31-
# endif
21+
# define CONVERT_DCMP_ARGS_TO_DF2_ARGS \
22+
VMOV_TO_DOUBLE(d0, r0, r1) \
23+
VMOV_TO_DOUBLE(d1, r2, r3)
3224
#else
3325
# define CONVERT_DCMP_ARGS_TO_DF2_ARGS
3426
#endif

‎compiler-rt/lib/builtins/arm/divdf3vfp.S‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,10 +20,10 @@ DEFINE_COMPILERRT_FUNCTION(__divdf3vfp)
2020
#if defined(COMPILER_RT_ARMHF_TARGET)
2121
vdiv.f64 d0, d0, d1
2222
#else
23-
vmov d6, r0, r1 // move first param from r0/r1 pair into d6
24-
vmov d7, r2, r3 // move second param from r2/r3 pair into d7
23+
VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
24+
VMOV_TO_DOUBLE(d7, r2, r3) // move second param from r2/r3 pair into d7
2525
vdiv.f64 d5, d6, d7
26-
vmov r0, r1, d5 // move result back to r0/r1 pair
26+
VMOV_FROM_DOUBLE(r0, r1, d5) // move result back to r0/r1 pair
2727
#endif
2828
bx lr
2929
END_COMPILERRT_FUNCTION(__divdf3vfp)

‎compiler-rt/lib/builtins/arm/eqdf2vfp.S‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,8 @@ DEFINE_COMPILERRT_FUNCTION(__eqdf2vfp)
2020
#if defined(COMPILER_RT_ARMHF_TARGET)
2121
vcmp.f64 d0, d1
2222
#else
23-
vmov d6, r0, r1 // load r0/r1 pair in double register
24-
vmov d7, r2, r3 // load r2/r3 pair in double register
23+
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
24+
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
2525
vcmp.f64 d6, d7
2626
#endif
2727
vmrs apsr_nzcv, fpscr

‎compiler-rt/lib/builtins/arm/extendsfdf2vfp.S‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ DEFINE_COMPILERRT_FUNCTION(__extendsfdf2vfp)
2323
#else
2424
vmov s15, r0 // load float register from R0
2525
vcvt.f64.f32 d7, s15 // convert single to double
26-
vmov r0, r1, d7 // return result in r0/r1 pair
26+
VMOV_FROM_DOUBLE(r0, r1, d7) // return result in r0/r1 pair
2727
#endif
2828
bx lr
2929
END_COMPILERRT_FUNCTION(__extendsfdf2vfp)

‎compiler-rt/lib/builtins/arm/fixdfsivfp.S‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ DEFINE_COMPILERRT_FUNCTION(__fixdfsivfp)
2222
vcvt.s32.f64 s0, d0
2323
vmov r0, s0
2424
#else
25-
vmov d7, r0, r1 // load double register from R0/R1
25+
VMOV_TO_DOUBLE(d7, r0, r1) // load double register from R0/R1
2626
vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15
2727
vmov r0, s15 // move s15 to result register
2828
#endif

‎compiler-rt/lib/builtins/arm/fixunsdfsivfp.S‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ DEFINE_COMPILERRT_FUNCTION(__fixunsdfsivfp)
2323
vcvt.u32.f64 s0, d0
2424
vmov r0, s0
2525
#else
26-
vmov d7, r0, r1 // load double register from R0/R1
26+
VMOV_TO_DOUBLE(d7, r0, r1) // load double register from R0/R1
2727
vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15
2828
vmov r0, s15 // move s15 to result register
2929
#endif

‎compiler-rt/lib/builtins/arm/floatsidfvfp.S‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ DEFINE_COMPILERRT_FUNCTION(__floatsidfvfp)
2424
#else
2525
vmov s15, r0 // move int to float register s15
2626
vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
27-
vmov r0, r1, d7 // move d7 to result register pair r0/r1
27+
VMOV_FROM_DOUBLE(r0, r1, d7) // move d7 to result register pair r0/r1
2828
#endif
2929
bx lr
3030
END_COMPILERRT_FUNCTION(__floatsidfvfp)

‎compiler-rt/lib/builtins/arm/floatunssidfvfp.S‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ DEFINE_COMPILERRT_FUNCTION(__floatunssidfvfp)
2424
#else
2525
vmov s15, r0 // move int to float register s15
2626
vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
27-
vmov r0, r1, d7 // move d7 to result register pair r0/r1
27+
VMOV_FROM_DOUBLE(r0, r1, r7) // move d7 to result register pair r0/r1
2828
#endif
2929
bx lr
3030
END_COMPILERRT_FUNCTION(__floatunssidfvfp)

‎compiler-rt/lib/builtins/arm/gedf2vfp.S‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ DEFINE_COMPILERRT_FUNCTION(__gedf2vfp)
2121
#if defined(COMPILER_RT_ARMHF_TARGET)
2222
vcmp.f64 d0, d1
2323
#else
24-
vmov d6, r0, r1 // load r0/r1 pair in double register
25-
vmov d7, r2, r3 // load r2/r3 pair in double register
24+
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
25+
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
2626
vcmp.f64 d6, d7
2727
#endif
2828
vmrs apsr_nzcv, fpscr

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