[CodeGen] Add Register::stackSlotIndex(). Replace uses of Register::stackSlot2Index. NFC (#125028)

Author: topperc

llvm/include/llvm/CodeGen/Register.h

@@ -98,6 +98,12 @@ class Register {
   /// register in a function will get the index 0.
   unsigned virtRegIndex() const { return virtReg2Index(Reg); }
 
+  /// Compute the frame index from a register value representing a stack slot.
+  int stackSlotIndex() const {
+    assert(isStack() && "Not a stack slot");
+    return static_cast<int>(Reg - MCRegister::FirstStackSlot);
+  }
+
   constexpr operator unsigned() const { return Reg; }
 
   constexpr unsigned id() const { return Reg; }

llvm/lib/CodeGen/ReachingDefAnalysis.cpp

@@ -346,8 +346,8 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, Register Reg) const {
          "Unexpected basic block number.");
   int LatestDef = ReachingDefDefaultVal;
 
-  if (Register::isStackSlot(Reg)) {
-    int FrameIndex = Register::stackSlot2Index(Reg);
+  if (Reg.isStack()) {
+    int FrameIndex = Reg.stackSlotIndex();
     for (int Def : MBBFrameObjsReachingDefs.lookup(MBBNumber).lookup(
              FrameIndex - ObjectIndexBegin)) {
       if (Def >= InstId)
@@ -617,8 +617,8 @@ MachineInstr *ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB,
   if (Last == MBB->end())
     return nullptr;
 
-  if (Register::isStackSlot(Reg)) {
-    int FrameIndex = Register::stackSlot2Index(Reg);
+  if (Reg.isStack()) {
+    int FrameIndex = Reg.stackSlotIndex();
     if (isFIDef(*Last, FrameIndex, TII))
       return &*Last;
   }

llvm/lib/CodeGen/StackSlotColoring.cpp

@@ -266,7 +266,7 @@ void StackSlotColoring::InitializeSlots() {
   for (auto *I : Intervals) {
     LiveInterval &li = I->second;
     LLVM_DEBUG(li.dump());
-    int FI = Register::stackSlot2Index(li.reg());
+    int FI = li.reg().stackSlotIndex();
     if (MFI->isDeadObjectIndex(FI))
       continue;
 
@@ -300,7 +300,7 @@ void StackSlotColoring::InitializeSlots() {
 int StackSlotColoring::ColorSlot(LiveInterval *li) {
   int Color = -1;
   bool Share = false;
-  int FI = Register::stackSlot2Index(li->reg());
+  int FI = li->reg().stackSlotIndex();
   uint8_t StackID = MFI->getStackID(FI);
 
   if (!DisableSharing) {
@@ -361,7 +361,7 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) {
   LLVM_DEBUG(dbgs() << "Color spill slot intervals:\n");
   bool Changed = false;
   for (LiveInterval *li : SSIntervals) {
-    int SS = Register::stackSlot2Index(li->reg());
+    int SS = li->reg().stackSlotIndex();
     int NewSS = ColorSlot(li);
     assert(NewSS >= 0 && "Stack coloring failed?");
     SlotMapping[SS] = NewSS;
@@ -373,7 +373,7 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) {
 
   LLVM_DEBUG(dbgs() << "\nSpill slots after coloring:\n");
   for (LiveInterval *li : SSIntervals) {
-    int SS = Register::stackSlot2Index(li->reg());
+    int SS = li->reg().stackSlotIndex();
     li->setWeight(SlotWeights[SS]);
   }
   // Sort them by new weight.

llvm/lib/CodeGen/TargetRegisterInfo.cpp

@@ -109,14 +109,14 @@ Printable printReg(Register Reg, const TargetRegisterInfo *TRI,
   return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
     if (!Reg)
       OS << "$noreg";
-    else if (Register::isStackSlot(Reg))
-      OS << "SS#" << Register::stackSlot2Index(Reg);
+    else if (Reg.isStack())
+      OS << "SS#" << Reg.stackSlotIndex();
     else if (Reg.isVirtual()) {
       StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
       if (Name != "") {
         OS << '%' << Name;
       } else {
-        OS << '%' << Register::virtReg2Index(Reg);
+        OS << '%' << Reg.virtRegIndex();
       }
     } else if (!TRI)
       OS << '$' << "physreg" << Reg.id();

llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp

@@ -88,7 +88,7 @@ bool AMDGPUMarkLastScratchLoad::runOnMachineFunction(MachineFunction &MF) {
       if (Segment.end.isBlock())
         continue;
 
-      const int FrameIndex = Register::stackSlot2Index(LI.reg());
+      const int FrameIndex = LI.reg().stackSlotIndex();
       MachineInstr *LastLoad = nullptr;
 
       MachineInstr *MISegmentEnd = SI->getInstructionFromIndex(Segment.end);

llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp

@@ -253,7 +253,7 @@ namespace {
                           /*Kill*/false, /*Dead*/false, /*Undef*/false,
                           /*EarlyClobber*/false, Sub);
         if (Reg.isStack()) {
-          int FI = llvm::Register::stackSlot2Index(Reg);
+          int FI = Reg.stackSlotIndex();
           return MachineOperand::CreateFI(FI);
         }
         llvm_unreachable("Cannot create MachineOperand");
@@ -1148,8 +1148,8 @@ void HCE::recordExtender(MachineInstr &MI, unsigned OpNum) {
   bool IsStore = MI.mayStore();
 
   // Fixed stack slots have negative indexes, and they cannot be used
-  // with TRI::stackSlot2Index and TRI::index2StackSlot. This is somewhat
-  // unfortunate, but should not be a frequent thing.
+  // with Register::stackSlotIndex and Register::index2StackSlot. This is
+  // somewhat unfortunate, but should not be a frequent thing.
   for (MachineOperand &Op : MI.operands())
     if (Op.isFI() && Op.getIndex() < 0)
       return;