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1 parent dfd4b74 commit dd55030Copy full SHA for dd55030
llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll
@@ -1,4 +1,4 @@
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-; RUN: llc < %s | FileCheck %s
+; RUN: llc -regalloc=greedy < %s | FileCheck %s
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; LSR shouldn't introduce more induction variables than needed, increasing
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; register pressure and therefore spilling. There is more room for improvement
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