Skip to content

Commit dd92609

Browse files
realqhctopperc
andauthored
[RISC-V] Add P-ext MC Support for Remaining Pair Operations (#159247)
This patch implements pages 21-24 from jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf Documentation: jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf Co-authored-by: Craig Topper <[email protected]>
1 parent a2efa7a commit dd92609

File tree

3 files changed

+599
-2
lines changed

3 files changed

+599
-2
lines changed

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

Lines changed: 258 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -132,6 +132,37 @@ class RVPNarrowingBase<bits<3> f, bit r, bits<4> funct4, dag outs, dag ins,
132132
let Inst{6-0} = OPC_OP_IMM_32.Value;
133133
}
134134

135+
// Common base for pair ops (non-widening nor narrowing)
136+
class RVPPairBase<bits<3> f, bit r, bit direction, dag outs, dag ins,
137+
string opcodestr, string argstr>
138+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
139+
bits<5> rs1;
140+
bits<5> rd;
141+
142+
let Inst{30-28} = f;
143+
let Inst{27} = r;
144+
let Inst{19-16} = rs1{4-1};
145+
let Inst{15} = direction;
146+
let Inst{14-12} = 0b110;
147+
let Inst{11-8} = rd{4-1};
148+
let Inst{7} = 0b0;
149+
let Inst{6-0} = OPC_OP_IMM_32.Value;
150+
}
151+
152+
// Common base for pair binary ops
153+
class RVPPairBinaryBase_rr<bits<3> f, bit r, bits<2> w, bit pack, bit direction,
154+
string opcodestr>
155+
: RVPPairBase<f, r, direction, (outs GPRPairRV32:$rd),
156+
(ins GPRPairRV32:$rs1, GPRPairRV32:$rs2), opcodestr,
157+
"$rd, $rs1, $rs2"> {
158+
bits<5> rs2;
159+
160+
let Inst{31} = 0b1;
161+
let Inst{26-25} = w;
162+
let Inst{24-21} = rs2{4-1};
163+
let Inst{20} = pack;
164+
}
165+
135166
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
136167
class RVPShift_ri<bits<3> f, bits<3> funct3, string opcodestr, Operand ImmType>
137168
: RVInstIBase<funct3, OPC_OP_IMM_32, (outs GPR:$rd),
@@ -249,6 +280,39 @@ class RVPNarrowingShiftB_ri<bits<3> f, string opcodestr>
249280
let Inst{23-20} = shamt;
250281
}
251282

283+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
284+
class RVPPairShift_ri<bits<3> f, string opcodestr, Operand ImmType,
285+
bit direction>
286+
: RVPPairBase<f, 0b0, direction, (outs GPRPairRV32:$rd),
287+
(ins GPRPairRV32:$rs1, ImmType:$shamt), opcodestr,
288+
"$rd, $rs1, $shamt"> {
289+
let Inst{31} = 0b0;
290+
}
291+
292+
class RVPPairShiftW_ri<bits<3> f, string opcodestr, bit direction = 0b0>
293+
: RVPPairShift_ri<f, opcodestr, uimm5, direction> {
294+
bits<5> shamt;
295+
296+
let Inst{26-25} = 0b01;
297+
let Inst{24-20} = shamt;
298+
}
299+
300+
class RVPPairShiftH_ri<bits<3> f, string opcodestr, bit direction = 0b0>
301+
: RVPPairShift_ri<f, opcodestr, uimm4, direction> {
302+
bits<4> shamt;
303+
304+
let Inst{26-24} = 0b001;
305+
let Inst{23-20} = shamt;
306+
}
307+
308+
class RVPPairShiftB_ri<bits<3> f, string opcodestr, bit direction = 0b0>
309+
: RVPPairShift_ri<f, opcodestr, uimm3, direction> {
310+
bits<3> shamt;
311+
312+
let Inst{26-23} = 0b0001;
313+
let Inst{22-20} = shamt;
314+
}
315+
252316
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
253317
class RVPNarrowingShift_rr<bits<3> f, bits<2> w, string opcodestr>
254318
: RVPNarrowingBase<f, 0b1, 0b1100, (outs GPR:$rd),
@@ -268,6 +332,18 @@ class RVPWideningShift_rr<bits<3> f, bits<2> w, string opcodestr>
268332
let Inst{27} = 0b1;
269333
}
270334

335+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
336+
class RVPPairShift_rr<bits<3> f, bits<2> w, string opcodestr,
337+
bit direction = 0b0>
338+
: RVPPairBase<f, 0b1, direction, (outs GPRPairRV32:$rd),
339+
(ins GPRPairRV32:$rs1, GPR:$rs2), opcodestr,
340+
"$rd, $rs1, $rs2"> {
341+
bits<5> rs2;
342+
343+
let Inst{26-25} = w;
344+
let Inst{24-20} = rs2;
345+
}
346+
271347
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
272348
class RVPUnary_ri<bits<2> w, bits<5> uf, string opcodestr>
273349
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
@@ -277,6 +353,15 @@ class RVPUnary_ri<bits<2> w, bits<5> uf, string opcodestr>
277353
let Inst{24-20} = uf;
278354
}
279355

356+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
357+
class RVPPairUnary_r<bits<2> w, bits<5> uf, string opcodestr>
358+
: RVPPairBase<0b110, 0b0, 0b0, (outs GPRPairRV32:$rd),
359+
(ins GPRPairRV32:$rs1), opcodestr, "$rd, $rs1"> {
360+
let Inst{31} = 0b0;
361+
let Inst{26-25} = w;
362+
let Inst{24-20} = uf;
363+
}
364+
280365
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
281366
class RVPBinaryScalar_rr<bits<3> f, bits<2> w, bits<3> funct3, string opcodestr>
282367
: RVInstRBase<funct3, OPC_OP_IMM_32, (outs GPR:$rd),
@@ -314,6 +399,22 @@ class RVPNarrowingBinary_rr<bits<3> f, bits<2> w, string opcodestr>
314399
let Inst{24-20} = rs2;
315400
}
316401

402+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
403+
class RVPPairBinary_rr<bits<4> f, bits<2> w, string opcodestr>
404+
: RVPPairBinaryBase_rr<f{3-1}, f{0}, w, 0b0, 0b0, opcodestr>;
405+
406+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
407+
class RVPPairBinaryShift_rr<bits<3> f, bits<2> w, string opcodestr>
408+
: RVPPairBinaryBase_rr<f, 0b0, w, 0b1, 0b0, opcodestr>;
409+
410+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
411+
class RVPPairBinaryPack_rr<bits<3> f, bits<2> w, string opcodestr>
412+
: RVPPairBinaryBase_rr<f, 0b0, w, 0b0, 0b1, opcodestr>;
413+
414+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
415+
class RVPPairBinaryExchanged_rr<bits<4> f, bits<2> w, string opcodestr>
416+
: RVPPairBinaryBase_rr<f{3-1}, f{0}, w, 0b1, 0b1, opcodestr>;
417+
317418
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
318419
class RVPTernary_rrr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
319420
: RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd_wb),
@@ -1196,4 +1297,161 @@ let Predicates = [HasStdExtP, IsRV32] in {
11961297
def PNCLIPR_BS : RVPNarrowingShift_rr<0b111, 0b00, "pnclipr.bs">;
11971298
def PNCLIPR_HS : RVPNarrowingShift_rr<0b111, 0b01, "pnclipr.hs">;
11981299
def NCLIPR : RVPNarrowingShift_rr<0b111, 0b11, "nclipr">;
1300+
1301+
def PSLLI_DB : RVPPairShiftB_ri<0b000, "pslli.db">;
1302+
def PSLLI_DH : RVPPairShiftH_ri<0b000, "pslli.dh">;
1303+
def PSLLI_DW : RVPPairShiftW_ri<0b000, "pslli.dw">;
1304+
1305+
def PSSLAI_DH : RVPPairShiftH_ri<0b101, "psslai.dh">;
1306+
def PSSLAI_DW : RVPPairShiftW_ri<0b101, "psslai.dw">;
1307+
1308+
def PSEXT_DH_B : RVPPairUnary_r<0b00, 0b00100, "psext.dh.b">;
1309+
def PSEXT_DW_B : RVPPairUnary_r<0b01, 0b00100, "psext.dw.b">;
1310+
1311+
def PSEXT_DW_H : RVPPairUnary_r<0b01, 0b00101, "psext.dw.h">;
1312+
1313+
def PSABS_DH : RVPPairUnary_r<0b00, 0b00111, "psabs.dh">;
1314+
def PSABS_DB : RVPPairUnary_r<0b10, 0b00111, "psabs.db">;
1315+
1316+
def PSLL_DHS : RVPPairShift_rr<0b000, 0b00, "psll.dhs">;
1317+
def PSLL_DWS : RVPPairShift_rr<0b000, 0b01, "psll.dws">;
1318+
def PSLL_DBS : RVPPairShift_rr<0b000, 0b10, "psll.dbs">;
1319+
1320+
def PADD_DHS : RVPPairShift_rr<0b001, 0b00, "padd.dhs">;
1321+
def PADD_DWS : RVPPairShift_rr<0b001, 0b01, "padd.dws">;
1322+
def PADD_DBS : RVPPairShift_rr<0b001, 0b10, "padd.dbs">;
1323+
1324+
def PSSHA_DHS : RVPPairShift_rr<0b110, 0b00, "pssha.dhs">;
1325+
def PSSHA_DWS : RVPPairShift_rr<0b110, 0b01, "pssha.dws">;
1326+
1327+
def PSSHAR_DHS : RVPPairShift_rr<0b111, 0b00, "psshar.dhs">;
1328+
def PSSHAR_DWS : RVPPairShift_rr<0b111, 0b01, "psshar.dws">;
1329+
1330+
def PSRLI_DB : RVPPairShiftB_ri<0b000, "psrli.db", 0b1>;
1331+
def PSRLI_DH : RVPPairShiftH_ri<0b000, "psrli.dh", 0b1>;
1332+
def PSRLI_DW : RVPPairShiftW_ri<0b000, "psrli.dw", 0b1>;
1333+
1334+
def PUSATI_DH : RVPPairShiftH_ri<0b010, "pusati.dh", 0b1>;
1335+
def PUSATI_DW : RVPPairShiftW_ri<0b010, "pusati.dw", 0b1>;
1336+
1337+
def PSRAI_DB : RVPPairShiftB_ri<0b100, "psrai.db", 0b1>;
1338+
def PSRAI_DH : RVPPairShiftH_ri<0b100, "psrai.dh", 0b1>;
1339+
def PSRAI_DW : RVPPairShiftW_ri<0b100, "psrai.dw", 0b1>;
1340+
1341+
def PSRARI_DH : RVPPairShiftH_ri<0b101, "psrari.dh", 0b1>;
1342+
def PSRARI_DW : RVPPairShiftW_ri<0b101, "psrari.dw", 0b1>;
1343+
1344+
def PSATI_DH : RVPPairShiftH_ri<0b110, "psati.dh", 0b1>;
1345+
def PSATI_DW : RVPPairShiftW_ri<0b110, "psati.dw", 0b1>;
1346+
1347+
def PSRL_DHS : RVPPairShift_rr<0b000, 0b00, "psrl.dhs", 0b1>;
1348+
def PSRL_DWS : RVPPairShift_rr<0b000, 0b01, "psrl.dws", 0b1>;
1349+
def PSRL_DBS : RVPPairShift_rr<0b000, 0b10, "psrl.dbs", 0b1>;
1350+
1351+
def PSRA_DHS : RVPPairShift_rr<0b100, 0b00, "psra.dhs", 0b1>;
1352+
def PSRA_DWS : RVPPairShift_rr<0b100, 0b01, "psra.dws", 0b1>;
1353+
def PSRA_DBS : RVPPairShift_rr<0b100, 0b10, "psra.dbs", 0b1>;
1354+
1355+
def PADD_DH : RVPPairBinary_rr<0b0000, 0b00, "padd.dh">;
1356+
def PADD_DW : RVPPairBinary_rr<0b0000, 0b01, "padd.dw">;
1357+
def PADD_DB : RVPPairBinary_rr<0b0000, 0b10, "padd.db">;
1358+
def ADDD : RVPPairBinary_rr<0b0000, 0b11, "addd">;
1359+
1360+
def PSADD_DH : RVPPairBinary_rr<0b0010, 0b00, "psadd.dh">;
1361+
def PSADD_DW : RVPPairBinary_rr<0b0010, 0b01, "psadd.dw">;
1362+
def PSADD_DB : RVPPairBinary_rr<0b0010, 0b10, "psadd.db">;
1363+
1364+
def PAADD_DH : RVPPairBinary_rr<0b0011, 0b00, "paadd.dh">;
1365+
def PAADD_DW : RVPPairBinary_rr<0b0011, 0b01, "paadd.dw">;
1366+
def PAADD_DB : RVPPairBinary_rr<0b0011, 0b10, "paadd.db">;
1367+
1368+
def PSADDU_DH : RVPPairBinary_rr<0b0110, 0b00, "psaddu.dh">;
1369+
def PSADDU_DW : RVPPairBinary_rr<0b0110, 0b01, "psaddu.dw">;
1370+
def PSADDU_DB : RVPPairBinary_rr<0b0110, 0b10, "psaddu.db">;
1371+
1372+
def PAADDU_DH : RVPPairBinary_rr<0b0111, 0b00, "paaddu.dh">;
1373+
def PAADDU_DW : RVPPairBinary_rr<0b0111, 0b01, "paaddu.dw">;
1374+
def PAADDU_DB : RVPPairBinary_rr<0b0111, 0b10, "paaddu.db">;
1375+
1376+
def PSUB_DH : RVPPairBinary_rr<0b1000, 0b00, "psub.dh">;
1377+
def PSUB_DW : RVPPairBinary_rr<0b1000, 0b01, "psub.dw">;
1378+
def PSUB_DB : RVPPairBinary_rr<0b1000, 0b10, "psub.db">;
1379+
def SUBD : RVPPairBinary_rr<0b1000, 0b11, "subd">;
1380+
1381+
def PDIF_DH : RVPPairBinary_rr<0b1001, 0b00, "pdif.dh">;
1382+
def PDIF_DB : RVPPairBinary_rr<0b1001, 0b10, "pdif.db">;
1383+
1384+
def PSSUB_DH : RVPPairBinary_rr<0b1010, 0b00, "pssub.dh">;
1385+
def PSSUB_DW : RVPPairBinary_rr<0b1010, 0b01, "pssub.dw">;
1386+
def PSSUB_DB : RVPPairBinary_rr<0b1010, 0b10, "pssub.db">;
1387+
1388+
def PASUB_DH : RVPPairBinary_rr<0b1011, 0b00, "pasub.dh">;
1389+
def PASUB_DW : RVPPairBinary_rr<0b1011, 0b01, "pasub.dw">;
1390+
def PASUB_DB : RVPPairBinary_rr<0b1011, 0b10, "pasub.db">;
1391+
1392+
def PDIFU_DH : RVPPairBinary_rr<0b1101, 0b00, "pdifu.dh">;
1393+
def PDIFU_DB : RVPPairBinary_rr<0b1101, 0b10, "pdifu.db">;
1394+
1395+
def PSSUBU_DH : RVPPairBinary_rr<0b1110, 0b00, "pssubu.dh">;
1396+
def PSSUBU_DW : RVPPairBinary_rr<0b1110, 0b01, "pssubu.dw">;
1397+
def PSSUBU_DB : RVPPairBinary_rr<0b1110, 0b10, "pssubu.db">;
1398+
1399+
def PASUBU_DH : RVPPairBinary_rr<0b1111, 0b00, "pasubu.dh">;
1400+
def PASUBU_DW : RVPPairBinary_rr<0b1111, 0b01, "pasubu.dw">;
1401+
def PASUBU_DB : RVPPairBinary_rr<0b1111, 0b10, "pasubu.db">;
1402+
1403+
def PSH1ADD_DH : RVPPairBinaryShift_rr<0b010, 0b00, "psh1add.dh">;
1404+
def PSH1ADD_DW : RVPPairBinaryShift_rr<0b010, 0b01, "psh1add.dw">;
1405+
1406+
def PSSH1SADD_DH : RVPPairBinaryShift_rr<0b011, 0b00, "pssh1sadd.dh">;
1407+
def PSSH1SADD_DW : RVPPairBinaryShift_rr<0b011, 0b01, "pssh1sadd.dw">;
1408+
1409+
def PPACK_DH : RVPPairBinaryPack_rr<0b000, 0b00, "ppack.dh">;
1410+
def PPACK_DW : RVPPairBinaryPack_rr<0b000, 0b01, "ppack.dw">;
1411+
1412+
def PPACKBT_DH : RVPPairBinaryPack_rr<0b001, 0b00, "ppackbt.dh">;
1413+
def PPACKBT_DW : RVPPairBinaryPack_rr<0b001, 0b01, "ppackbt.dw">;
1414+
1415+
def PPACKTB_DH : RVPPairBinaryPack_rr<0b010, 0b00, "ppacktb.dh">;
1416+
def PPACKTB_DW : RVPPairBinaryPack_rr<0b010, 0b01, "ppacktb.dw">;
1417+
1418+
def PPACKT_DH : RVPPairBinaryPack_rr<0b011, 0b00, "ppackt.dh">;
1419+
def PPACKT_DW : RVPPairBinaryPack_rr<0b011, 0b01, "ppackt.dw">;
1420+
1421+
def PAS_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b00, "pas.dhx">;
1422+
def PSA_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b10, "psa.dhx">;
1423+
1424+
def PSAS_DHX : RVPPairBinaryExchanged_rr<0b0010, 0b00, "psas.dhx">;
1425+
def PSSA_DHX : RVPPairBinaryExchanged_rr<0b0010, 0b10, "pssa.dhx">;
1426+
1427+
def PAAX_DHX : RVPPairBinaryExchanged_rr<0b0011, 0b00, "paax.dhx">;
1428+
def PASA_DHX : RVPPairBinaryExchanged_rr<0b0011, 0b10, "pasa.dhx">;
1429+
1430+
def PMSEQ_DH : RVPPairBinaryExchanged_rr<0b1000, 0b00, "pmseq.dh">;
1431+
def PMSEQ_DW : RVPPairBinaryExchanged_rr<0b1000, 0b01, "pmseq.dw">;
1432+
def PMSEQ_DB : RVPPairBinaryExchanged_rr<0b1000, 0b10, "pmseq.db">;
1433+
1434+
def PMSLT_DH : RVPPairBinaryExchanged_rr<0b1010, 0b00, "pmslt.dh">;
1435+
def PMSLT_DW : RVPPairBinaryExchanged_rr<0b1010, 0b01, "pmslt.dw">;
1436+
def PMSLT_DB : RVPPairBinaryExchanged_rr<0b1010, 0b10, "pmslt.db">;
1437+
1438+
def PMSLTU_DH : RVPPairBinaryExchanged_rr<0b1011, 0b00, "pmsltu.dh">;
1439+
def PMSLTU_DW : RVPPairBinaryExchanged_rr<0b1011, 0b01, "pmsltu.dw">;
1440+
def PMSLTU_DB : RVPPairBinaryExchanged_rr<0b1011, 0b10, "pmsltu.db">;
1441+
1442+
def PMIN_DH : RVPPairBinaryExchanged_rr<0b1100, 0b00, "pmin.dh">;
1443+
def PMIN_DW : RVPPairBinaryExchanged_rr<0b1100, 0b01, "pmin.dw">;
1444+
def PMIN_DB : RVPPairBinaryExchanged_rr<0b1100, 0b10, "pmin.db">;
1445+
1446+
def PMINU_DH : RVPPairBinaryExchanged_rr<0b1101, 0b00, "pminu.dh">;
1447+
def PMINU_DW : RVPPairBinaryExchanged_rr<0b1101, 0b01, "pminu.dw">;
1448+
def PMINU_DB : RVPPairBinaryExchanged_rr<0b1101, 0b10, "pminu.db">;
1449+
1450+
def PMAX_DH : RVPPairBinaryExchanged_rr<0b1110, 0b00, "pmax.dh">;
1451+
def PMAX_DW : RVPPairBinaryExchanged_rr<0b1110, 0b01, "pmax.dw">;
1452+
def PMAX_DB : RVPPairBinaryExchanged_rr<0b1110, 0b10, "pmax.db">;
1453+
1454+
def PMAXU_DH : RVPPairBinaryExchanged_rr<0b1111, 0b00, "pmaxu.dh">;
1455+
def PMAXU_DW : RVPPairBinaryExchanged_rr<0b1111, 0b01, "pmaxu.dw">;
1456+
def PMAXU_DB : RVPPairBinaryExchanged_rr<0b1111, 0b10, "pmaxu.db">;
11991457
} // Predicates = [HasStdExtP, IsRV32]

llvm/test/MC/RISCV/invalid-instruction-spellcheck.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,10 +22,10 @@ fl ft0, 0(sp)
2222
# CHECK-RV64IF: did you mean: flw, la, lb, ld, lh, li, lw
2323
# CHECK-NEXT: fl ft0, 0(sp)
2424

25-
addd x1, x1, x1
25+
addc x1, x1, x1
2626
# CHECK-RV32: did you mean: add, addi
2727
# CHECK-RV64: did you mean: add, addi, addw
28-
# CHECK-NEXT: addd x1, x1, x1
28+
# CHECK-NEXT: addc x1, x1, x1
2929

3030
vm x0, x0
3131
# CHECK: did you mean: mv

0 commit comments

Comments
 (0)