Skip to content

Commit ddcf5d5

Browse files
committed
Drop extra VT
1 parent 6b380b0 commit ddcf5d5

File tree

1 file changed

+1
-1
lines changed

1 file changed

+1
-1
lines changed

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30044,7 +30044,7 @@ SDValue AArch64TargetLowering::LowerFixedLengthVECTOR_SHUFFLEToSVE(
3004430044
DAG.getConstant(Intrinsic::aarch64_sve_dup_laneq, DL, MVT::i64);
3004530045
return convertFromScalableVector(
3004630046
DAG, VT,
30047-
DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, {ContainerVT, MVT::i64},
30047+
DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, ContainerVT,
3004830048
{IID, Op1,
3004930049
DAG.getConstant(*Lane, DL, MVT::i64,
3005030050
/*isTarget=*/true)}));

0 commit comments

Comments
 (0)