fix RAC for Zn4WriteVPERMPSYrm

NexusXe · NexusXe · commit de0daad87f44 · 2025-10-01T14:15:59.000-05:00
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver4.td b/llvm/lib/Target/X86/X86ScheduleZnver4.td
@@ -1395,7 +1395,7 @@ def : InstRW<[Zn4WriteVPERMPSYrr], (instrs VPERMPSYrr)>;
 
 def Zn4WriteVPERMPSYrm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
   let Latency = !add(Znver4Model.VecLoadLatency, Zn4WriteVPERMPSYrr.Latency);
-  let ReleaseAtCycles = [1];
+  let ReleaseAtCycles = [1, 1, 1];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVPERMPSYrm], (instrs VPERMPSYrm)>;

Original file line number	Diff line number	Diff line change
`@@ -1395,7 +1395,7 @@ def : InstRW<[Zn4WriteVPERMPSYrr], (instrs VPERMPSYrr)>;`
`1395`	`1395`
`1396`	`1396`	`def Zn4WriteVPERMPSYrm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {`
`1397`	`1397`	`let Latency = !add(Znver4Model.VecLoadLatency, Zn4WriteVPERMPSYrr.Latency);`
`1398`		`- let ReleaseAtCycles = [1];`
	`1398`	`+ let ReleaseAtCycles = [1, 1, 1];`
`1399`	`1399`	`let NumMicroOps = 1;`
`1400`	`1400`	`}`
`1401`	`1401`	`def : InstRW<[Zn4WriteVPERMPSYrm], (instrs VPERMPSYrm)>;`