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[X86][PowerPC][AArch64]: Updated tests
1 parent 5218588 commit de10f4a

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‎llvm/test/CodeGen/AArch64/bsl.ll‎

Lines changed: 56 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -32,19 +32,17 @@ define <1 x i64> @bsl_v1i64(<1 x i64> %0, <1 x i64> %1, <1 x i64> %2) {
3232
define <1 x i64> @nbsl_v1i64(<1 x i64> %0, <1 x i64> %1, <1 x i64> %2) {
3333
; NEON-LABEL: nbsl_v1i64:
3434
; NEON: // %bb.0:
35-
; NEON-NEXT: and v0.8b, v2.8b, v0.8b
36-
; NEON-NEXT: bic v1.8b, v1.8b, v2.8b
35+
; NEON-NEXT: bif v0.8b, v1.8b, v2.8b
3736
; NEON-NEXT: mvn v0.8b, v0.8b
38-
; NEON-NEXT: bic v0.8b, v0.8b, v1.8b
3937
; NEON-NEXT: ret
4038
;
4139
; SVE2-LABEL: nbsl_v1i64:
4240
; SVE2: // %bb.0:
4341
; SVE2-NEXT: // kill: def $d0 killed $d0 def $z0
4442
; SVE2-NEXT: // kill: def $d2 killed $d2 def $z2
45-
; SVE2-NEXT: bic v1.8b, v1.8b, v2.8b
46-
; SVE2-NEXT: nbsl z0.d, z0.d, z2.d, z2.d
47-
; SVE2-NEXT: bic v0.8b, v0.8b, v1.8b
43+
; SVE2-NEXT: // kill: def $d1 killed $d1 def $z1
44+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
45+
; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0
4846
; SVE2-NEXT: ret
4947
%4 = and <1 x i64> %2, %0
5048
%5 = xor <1 x i64> %2, splat (i64 -1)
@@ -80,8 +78,9 @@ define <1 x i64> @bsl1n_v1i64(<1 x i64> %0, <1 x i64> %1, <1 x i64> %2) {
8078
define <1 x i64> @bsl2n_v1i64(<1 x i64> %0, <1 x i64> %1, <1 x i64> %2) {
8179
; NEON-LABEL: bsl2n_v1i64:
8280
; NEON: // %bb.0:
83-
; NEON-NEXT: mvn v1.8b, v1.8b
84-
; NEON-NEXT: bif v0.8b, v1.8b, v2.8b
81+
; NEON-NEXT: and v0.8b, v2.8b, v0.8b
82+
; NEON-NEXT: orr v1.8b, v2.8b, v1.8b
83+
; NEON-NEXT: orn v0.8b, v0.8b, v1.8b
8584
; NEON-NEXT: ret
8685
;
8786
; SVE2-LABEL: bsl2n_v1i64:
@@ -119,19 +118,17 @@ define <2 x i64> @bsl_v2i64(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
119118
define <2 x i64> @nbsl_v2i64(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
120119
; NEON-LABEL: nbsl_v2i64:
121120
; NEON: // %bb.0:
122-
; NEON-NEXT: and v0.16b, v2.16b, v0.16b
123-
; NEON-NEXT: bic v1.16b, v1.16b, v2.16b
121+
; NEON-NEXT: bif v0.16b, v1.16b, v2.16b
124122
; NEON-NEXT: mvn v0.16b, v0.16b
125-
; NEON-NEXT: bic v0.16b, v0.16b, v1.16b
126123
; NEON-NEXT: ret
127124
;
128125
; SVE2-LABEL: nbsl_v2i64:
129126
; SVE2: // %bb.0:
130127
; SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
131128
; SVE2-NEXT: // kill: def $q2 killed $q2 def $z2
132-
; SVE2-NEXT: bic v1.16b, v1.16b, v2.16b
133-
; SVE2-NEXT: nbsl z0.d, z0.d, z2.d, z2.d
134-
; SVE2-NEXT: bic v0.16b, v0.16b, v1.16b
129+
; SVE2-NEXT: // kill: def $q1 killed $q1 def $z1
130+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
131+
; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0
135132
; SVE2-NEXT: ret
136133
%4 = and <2 x i64> %2, %0
137134
%5 = xor <2 x i64> %2, splat (i64 -1)
@@ -167,8 +164,9 @@ define <2 x i64> @bsl1n_v2i64(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
167164
define <2 x i64> @bsl2n_v2i64(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
168165
; NEON-LABEL: bsl2n_v2i64:
169166
; NEON: // %bb.0:
170-
; NEON-NEXT: mvn v1.16b, v1.16b
171-
; NEON-NEXT: bif v0.16b, v1.16b, v2.16b
167+
; NEON-NEXT: and v0.16b, v2.16b, v0.16b
168+
; NEON-NEXT: orr v1.16b, v2.16b, v1.16b
169+
; NEON-NEXT: orn v0.16b, v0.16b, v1.16b
172170
; NEON-NEXT: ret
173171
;
174172
; SVE2-LABEL: bsl2n_v2i64:
@@ -191,18 +189,17 @@ define <2 x i64> @bsl2n_v2i64(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
191189
define <8 x i8> @nbsl_v8i8(<8 x i8> %0, <8 x i8> %1, <8 x i8> %2) {
192190
; NEON-LABEL: nbsl_v8i8:
193191
; NEON: // %bb.0:
194-
; NEON-NEXT: and v3.8b, v2.8b, v1.8b
195-
; NEON-NEXT: and v0.8b, v2.8b, v0.8b
196-
; NEON-NEXT: orn v1.8b, v3.8b, v1.8b
197-
; NEON-NEXT: bic v0.8b, v1.8b, v0.8b
192+
; NEON-NEXT: bif v0.8b, v1.8b, v2.8b
193+
; NEON-NEXT: mvn v0.8b, v0.8b
198194
; NEON-NEXT: ret
199195
;
200196
; SVE2-LABEL: nbsl_v8i8:
201197
; SVE2: // %bb.0:
202-
; SVE2-NEXT: and v3.8b, v2.8b, v1.8b
203-
; SVE2-NEXT: and v0.8b, v2.8b, v0.8b
204-
; SVE2-NEXT: orn v1.8b, v3.8b, v1.8b
205-
; SVE2-NEXT: bic v0.8b, v1.8b, v0.8b
198+
; SVE2-NEXT: // kill: def $d0 killed $d0 def $z0
199+
; SVE2-NEXT: // kill: def $d2 killed $d2 def $z2
200+
; SVE2-NEXT: // kill: def $d1 killed $d1 def $z1
201+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
202+
; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0
206203
; SVE2-NEXT: ret
207204
%4 = and <8 x i8> %2, %0
208205
%5 = xor <8 x i8> %2, splat (i8 -1)
@@ -215,18 +212,17 @@ define <8 x i8> @nbsl_v8i8(<8 x i8> %0, <8 x i8> %1, <8 x i8> %2) {
215212
define <4 x i16> @nbsl_v4i16(<4 x i16> %0, <4 x i16> %1, <4 x i16> %2) {
216213
; NEON-LABEL: nbsl_v4i16:
217214
; NEON: // %bb.0:
218-
; NEON-NEXT: and v3.8b, v2.8b, v1.8b
219-
; NEON-NEXT: and v0.8b, v2.8b, v0.8b
220-
; NEON-NEXT: orn v1.8b, v3.8b, v1.8b
221-
; NEON-NEXT: bic v0.8b, v1.8b, v0.8b
215+
; NEON-NEXT: bif v0.8b, v1.8b, v2.8b
216+
; NEON-NEXT: mvn v0.8b, v0.8b
222217
; NEON-NEXT: ret
223218
;
224219
; SVE2-LABEL: nbsl_v4i16:
225220
; SVE2: // %bb.0:
226-
; SVE2-NEXT: and v3.8b, v2.8b, v1.8b
227-
; SVE2-NEXT: and v0.8b, v2.8b, v0.8b
228-
; SVE2-NEXT: orn v1.8b, v3.8b, v1.8b
229-
; SVE2-NEXT: bic v0.8b, v1.8b, v0.8b
221+
; SVE2-NEXT: // kill: def $d0 killed $d0 def $z0
222+
; SVE2-NEXT: // kill: def $d2 killed $d2 def $z2
223+
; SVE2-NEXT: // kill: def $d1 killed $d1 def $z1
224+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
225+
; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0
230226
; SVE2-NEXT: ret
231227
%4 = and <4 x i16> %2, %0
232228
%5 = xor <4 x i16> %2, splat (i16 -1)
@@ -239,19 +235,17 @@ define <4 x i16> @nbsl_v4i16(<4 x i16> %0, <4 x i16> %1, <4 x i16> %2) {
239235
define <2 x i32> @nbsl_v2i32(<2 x i32> %0, <2 x i32> %1, <2 x i32> %2) {
240236
; NEON-LABEL: nbsl_v2i32:
241237
; NEON: // %bb.0:
242-
; NEON-NEXT: and v0.8b, v2.8b, v0.8b
243-
; NEON-NEXT: bic v1.8b, v1.8b, v2.8b
238+
; NEON-NEXT: bif v0.8b, v1.8b, v2.8b
244239
; NEON-NEXT: mvn v0.8b, v0.8b
245-
; NEON-NEXT: bic v0.8b, v0.8b, v1.8b
246240
; NEON-NEXT: ret
247241
;
248242
; SVE2-LABEL: nbsl_v2i32:
249243
; SVE2: // %bb.0:
250244
; SVE2-NEXT: // kill: def $d0 killed $d0 def $z0
251245
; SVE2-NEXT: // kill: def $d2 killed $d2 def $z2
252-
; SVE2-NEXT: bic v1.8b, v1.8b, v2.8b
253-
; SVE2-NEXT: nbsl z0.d, z0.d, z2.d, z2.d
254-
; SVE2-NEXT: bic v0.8b, v0.8b, v1.8b
246+
; SVE2-NEXT: // kill: def $d1 killed $d1 def $z1
247+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
248+
; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0
255249
; SVE2-NEXT: ret
256250
%4 = and <2 x i32> %2, %0
257251
%5 = xor <2 x i32> %2, splat (i32 -1)
@@ -264,18 +258,17 @@ define <2 x i32> @nbsl_v2i32(<2 x i32> %0, <2 x i32> %1, <2 x i32> %2) {
264258
define <16 x i8> @nbsl_v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) {
265259
; NEON-LABEL: nbsl_v16i8:
266260
; NEON: // %bb.0:
267-
; NEON-NEXT: and v3.16b, v2.16b, v1.16b
268-
; NEON-NEXT: and v0.16b, v2.16b, v0.16b
269-
; NEON-NEXT: orn v1.16b, v3.16b, v1.16b
270-
; NEON-NEXT: bic v0.16b, v1.16b, v0.16b
261+
; NEON-NEXT: bif v0.16b, v1.16b, v2.16b
262+
; NEON-NEXT: mvn v0.16b, v0.16b
271263
; NEON-NEXT: ret
272264
;
273265
; SVE2-LABEL: nbsl_v16i8:
274266
; SVE2: // %bb.0:
275-
; SVE2-NEXT: and v3.16b, v2.16b, v1.16b
276-
; SVE2-NEXT: and v0.16b, v2.16b, v0.16b
277-
; SVE2-NEXT: orn v1.16b, v3.16b, v1.16b
278-
; SVE2-NEXT: bic v0.16b, v1.16b, v0.16b
267+
; SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
268+
; SVE2-NEXT: // kill: def $q2 killed $q2 def $z2
269+
; SVE2-NEXT: // kill: def $q1 killed $q1 def $z1
270+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
271+
; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0
279272
; SVE2-NEXT: ret
280273
%4 = and <16 x i8> %2, %0
281274
%5 = xor <16 x i8> %2, splat (i8 -1)
@@ -288,18 +281,17 @@ define <16 x i8> @nbsl_v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) {
288281
define <8 x i16> @nbsl_v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) {
289282
; NEON-LABEL: nbsl_v8i16:
290283
; NEON: // %bb.0:
291-
; NEON-NEXT: and v3.16b, v2.16b, v1.16b
292-
; NEON-NEXT: and v0.16b, v2.16b, v0.16b
293-
; NEON-NEXT: orn v1.16b, v3.16b, v1.16b
294-
; NEON-NEXT: bic v0.16b, v1.16b, v0.16b
284+
; NEON-NEXT: bif v0.16b, v1.16b, v2.16b
285+
; NEON-NEXT: mvn v0.16b, v0.16b
295286
; NEON-NEXT: ret
296287
;
297288
; SVE2-LABEL: nbsl_v8i16:
298289
; SVE2: // %bb.0:
299-
; SVE2-NEXT: and v3.16b, v2.16b, v1.16b
300-
; SVE2-NEXT: and v0.16b, v2.16b, v0.16b
301-
; SVE2-NEXT: orn v1.16b, v3.16b, v1.16b
302-
; SVE2-NEXT: bic v0.16b, v1.16b, v0.16b
290+
; SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
291+
; SVE2-NEXT: // kill: def $q2 killed $q2 def $z2
292+
; SVE2-NEXT: // kill: def $q1 killed $q1 def $z1
293+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
294+
; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0
303295
; SVE2-NEXT: ret
304296
%4 = and <8 x i16> %2, %0
305297
%5 = xor <8 x i16> %2, splat (i16 -1)
@@ -312,19 +304,17 @@ define <8 x i16> @nbsl_v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) {
312304
define <4 x i32> @nbsl_v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) {
313305
; NEON-LABEL: nbsl_v4i32:
314306
; NEON: // %bb.0:
315-
; NEON-NEXT: and v0.16b, v2.16b, v0.16b
316-
; NEON-NEXT: bic v1.16b, v1.16b, v2.16b
307+
; NEON-NEXT: bif v0.16b, v1.16b, v2.16b
317308
; NEON-NEXT: mvn v0.16b, v0.16b
318-
; NEON-NEXT: bic v0.16b, v0.16b, v1.16b
319309
; NEON-NEXT: ret
320310
;
321311
; SVE2-LABEL: nbsl_v4i32:
322312
; SVE2: // %bb.0:
323313
; SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
324314
; SVE2-NEXT: // kill: def $q2 killed $q2 def $z2
325-
; SVE2-NEXT: bic v1.16b, v1.16b, v2.16b
326-
; SVE2-NEXT: nbsl z0.d, z0.d, z2.d, z2.d
327-
; SVE2-NEXT: bic v0.16b, v0.16b, v1.16b
315+
; SVE2-NEXT: // kill: def $q1 killed $q1 def $z1
316+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z2.d
317+
; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0
328318
; SVE2-NEXT: ret
329319
%4 = and <4 x i32> %2, %0
330320
%5 = xor <4 x i32> %2, splat (i32 -1)
@@ -481,14 +471,16 @@ define <2 x i64> @nand_q(<2 x i64> %0, <2 x i64> %1) #0 {
481471
define <2 x i64> @nor_q(<2 x i64> %0, <2 x i64> %1) #0 {
482472
; NEON-LABEL: nor_q:
483473
; NEON: // %bb.0:
484-
; NEON-NEXT: mvn v1.16b, v1.16b
485-
; NEON-NEXT: bic v0.16b, v1.16b, v0.16b
474+
; NEON-NEXT: orr v0.16b, v1.16b, v0.16b
475+
; NEON-NEXT: mvn v0.16b, v0.16b
486476
; NEON-NEXT: ret
487477
;
488478
; SVE2-LABEL: nor_q:
489479
; SVE2: // %bb.0:
490-
; SVE2-NEXT: mvn v1.16b, v1.16b
491-
; SVE2-NEXT: bic v0.16b, v1.16b, v0.16b
480+
; SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
481+
; SVE2-NEXT: // kill: def $q1 killed $q1 def $z1
482+
; SVE2-NEXT: nbsl z0.d, z0.d, z1.d, z0.d
483+
; SVE2-NEXT: // kill: def $q0 killed $q0 killed $z0
492484
; SVE2-NEXT: ret
493485
%3 = or <2 x i64> %1, %0
494486
%4 = xor <2 x i64> %3, splat (i64 -1)

‎llvm/test/CodeGen/AArch64/build-vector-dup-simd.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -117,10 +117,10 @@ entry:
117117
define <1 x float> @dup_v1i32_ueq(float %a, float %b) {
118118
; CHECK-NOFULLFP16-LABEL: dup_v1i32_ueq:
119119
; CHECK-NOFULLFP16: // %bb.0: // %entry
120-
; CHECK-NOFULLFP16-NEXT: fcmgt s2, s1, s0
121-
; CHECK-NOFULLFP16-NEXT: fcmgt s0, s0, s1
122-
; CHECK-NOFULLFP16-NEXT: mvn v1.8b, v2.8b
123-
; CHECK-NOFULLFP16-NEXT: bic v0.8b, v1.8b, v0.8b
120+
; CHECK-NOFULLFP16-NEXT: fcmgt s2, s0, s1
121+
; CHECK-NOFULLFP16-NEXT: fcmgt s0, s1, s0
122+
; CHECK-NOFULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b
123+
; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b
124124
; CHECK-NOFULLFP16-NEXT: ret
125125
;
126126
; CHECK-NONANS-LABEL: dup_v1i32_ueq:
@@ -130,10 +130,10 @@ define <1 x float> @dup_v1i32_ueq(float %a, float %b) {
130130
;
131131
; CHECK-FULLFP16-LABEL: dup_v1i32_ueq:
132132
; CHECK-FULLFP16: // %bb.0: // %entry
133-
; CHECK-FULLFP16-NEXT: fcmgt s2, s1, s0
134-
; CHECK-FULLFP16-NEXT: fcmgt s0, s0, s1
135-
; CHECK-FULLFP16-NEXT: mvn v1.8b, v2.8b
136-
; CHECK-FULLFP16-NEXT: bic v0.8b, v1.8b, v0.8b
133+
; CHECK-FULLFP16-NEXT: fcmgt s2, s0, s1
134+
; CHECK-FULLFP16-NEXT: fcmgt s0, s1, s0
135+
; CHECK-FULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b
136+
; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b
137137
; CHECK-FULLFP16-NEXT: ret
138138
entry:
139139
%0 = fcmp ueq float %a, %b
@@ -260,10 +260,10 @@ entry:
260260
define <1 x float> @dup_v1i32_uno(float %a, float %b) {
261261
; CHECK-LABEL: dup_v1i32_uno:
262262
; CHECK: // %bb.0: // %entry
263-
; CHECK-NEXT: fcmgt s2, s1, s0
264-
; CHECK-NEXT: fcmge s0, s0, s1
265-
; CHECK-NEXT: mvn v1.8b, v2.8b
266-
; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
263+
; CHECK-NEXT: fcmge s2, s0, s1
264+
; CHECK-NEXT: fcmgt s0, s1, s0
265+
; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
266+
; CHECK-NEXT: mvn v0.8b, v0.8b
267267
; CHECK-NEXT: ret
268268
entry:
269269
%0 = fcmp uno float %a, %b

‎llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll‎

Lines changed: 14 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -563,13 +563,13 @@ define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
563563
; CHECK-CVT-SD-NEXT: mvn v0.8b, v0.8b
564564
; CHECK-CVT-SD-NEXT: ret
565565
;
566-
; CHECK-FP16-SD-LABEL: test_fcmp_ueq:
567-
; CHECK-FP16-SD: // %bb.0:
568-
; CHECK-FP16-SD-NEXT: fcmgt v2.4h, v1.4h, v0.4h
569-
; CHECK-FP16-SD-NEXT: fcmgt v0.4h, v0.4h, v1.4h
570-
; CHECK-FP16-SD-NEXT: mvn v1.8b, v2.8b
571-
; CHECK-FP16-SD-NEXT: bic v0.8b, v1.8b, v0.8b
572-
; CHECK-FP16-SD-NEXT: ret
566+
; CHECK-FP16-LABEL: test_fcmp_ueq:
567+
; CHECK-FP16: // %bb.0:
568+
; CHECK-FP16-NEXT: fcmgt v2.4h, v0.4h, v1.4h
569+
; CHECK-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h
570+
; CHECK-FP16-NEXT: orr v0.8b, v0.8b, v2.8b
571+
; CHECK-FP16-NEXT: mvn v0.8b, v0.8b
572+
; CHECK-FP16-NEXT: ret
573573
;
574574
; CHECK-CVT-GI-LABEL: test_fcmp_ueq:
575575
; CHECK-CVT-GI: // %bb.0:
@@ -581,14 +581,6 @@ define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
581581
; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b
582582
; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
583583
; CHECK-CVT-GI-NEXT: ret
584-
;
585-
; CHECK-FP16-GI-LABEL: test_fcmp_ueq:
586-
; CHECK-FP16-GI: // %bb.0:
587-
; CHECK-FP16-GI-NEXT: fcmgt v2.4h, v0.4h, v1.4h
588-
; CHECK-FP16-GI-NEXT: fcmgt v0.4h, v1.4h, v0.4h
589-
; CHECK-FP16-GI-NEXT: orr v0.8b, v0.8b, v2.8b
590-
; CHECK-FP16-GI-NEXT: mvn v0.8b, v0.8b
591-
; CHECK-FP16-GI-NEXT: ret
592584

593585
%1 = fcmp ueq <4 x half> %a, %b
594586
ret <4 x i1> %1
@@ -722,13 +714,13 @@ define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
722714
; CHECK-CVT-SD-NEXT: mvn v0.8b, v0.8b
723715
; CHECK-CVT-SD-NEXT: ret
724716
;
725-
; CHECK-FP16-SD-LABEL: test_fcmp_uno:
726-
; CHECK-FP16-SD: // %bb.0:
727-
; CHECK-FP16-SD-NEXT: fcmgt v2.4h, v1.4h, v0.4h
728-
; CHECK-FP16-SD-NEXT: fcmge v0.4h, v0.4h, v1.4h
729-
; CHECK-FP16-SD-NEXT: mvn v1.8b, v2.8b
730-
; CHECK-FP16-SD-NEXT: bic v0.8b, v1.8b, v0.8b
731-
; CHECK-FP16-SD-NEXT: ret
717+
; CHECK-FP16-LABEL: test_fcmp_uno:
718+
; CHECK-FP16: // %bb.0:
719+
; CHECK-FP16-NEXT: fcmge v2.4h, v0.4h, v1.4h
720+
; CHECK-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h
721+
; CHECK-FP16-NEXT: orr v0.8b, v0.8b, v2.8b
722+
; CHECK-FP16-NEXT: mvn v0.8b, v0.8b
723+
; CHECK-FP16-NEXT: ret
732724
;
733725
; CHECK-CVT-GI-LABEL: test_fcmp_uno:
734726
; CHECK-CVT-GI: // %bb.0:
@@ -740,14 +732,6 @@ define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
740732
; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b
741733
; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s
742734
; CHECK-CVT-GI-NEXT: ret
743-
;
744-
; CHECK-FP16-GI-LABEL: test_fcmp_uno:
745-
; CHECK-FP16-GI: // %bb.0:
746-
; CHECK-FP16-GI-NEXT: fcmge v2.4h, v0.4h, v1.4h
747-
; CHECK-FP16-GI-NEXT: fcmgt v0.4h, v1.4h, v0.4h
748-
; CHECK-FP16-GI-NEXT: orr v0.8b, v0.8b, v2.8b
749-
; CHECK-FP16-GI-NEXT: mvn v0.8b, v0.8b
750-
; CHECK-FP16-GI-NEXT: ret
751735

752736
%1 = fcmp uno <4 x half> %a, %b
753737
ret <4 x i1> %1

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