@@ -2136,23 +2136,6 @@ multiclass VPseudoBinaryRoundingMode<VReg RetClass,
21362136}
21372137
21382138
2139- multiclass VPseudoBinaryM<VReg RetClass,
2140- VReg Op1Class,
2141- DAGOperand Op2Class,
2142- LMULInfo MInfo,
2143- string Constraint = "",
2144- bits<2> TargetConstraintType = 1,
2145- bit Commutable = 0> {
2146- let VLMul = MInfo.value, isCommutable = Commutable in {
2147- def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
2148- Constraint, TargetConstraintType>;
2149- let ForceTailAgnostic = true in
2150- def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
2151- Op2Class, Constraint, TargetConstraintType>,
2152- RISCVMaskedPseudo<MaskIdx=3>;
2153- }
2154- }
2155-
21562139multiclass VPseudoBinaryEmul<VReg RetClass,
21572140 VReg Op1Class,
21582141 DAGOperand Op2Class,
@@ -2633,28 +2616,35 @@ multiclass PseudoVEXT_VF8 {
26332616// lowest-numbered part of the source register group".
26342617// With LMUL<=1 the source and dest occupy a single register so any overlap
26352618// is in the lowest-numbered part.
2636- multiclass VPseudoBinaryM_VV<LMULInfo m, bits<2> TargetConstraintType = 1,
2637- bit Commutable = 0> {
2638- defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
2619+ multiclass VPseudoBinaryM<DAGOperand Op2Class, LMULInfo m, bit Commutable = 0> {
2620+ let VLMul = m.value, isCommutable = Commutable in {
2621+ def "_" # m.MX :
2622+ VPseudoBinaryNoMask<VR, m.vrclass, Op2Class,
2623+ !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),
2624+ TargetConstraintType = 2>;
2625+ let ForceTailAgnostic = true in
2626+ def "_" # m.MX # "_MASK" :
2627+ VPseudoBinaryMOutMask<VR, m.vrclass, Op2Class,
26392628 !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),
2640- TargetConstraintType, Commutable=Commutable>;
2629+ TargetConstraintType = 2>,
2630+ RISCVMaskedPseudo<MaskIdx=3>;
2631+ }
26412632}
26422633
2643- multiclass VPseudoBinaryM_VX<LMULInfo m, bits<2> TargetConstraintType = 1> {
2644- defm "_VX" :
2645- VPseudoBinaryM<VR, m.vrclass, GPR, m,
2646- !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
2634+ multiclass VPseudoBinaryM_VV<LMULInfo m, bit Commutable = 0> {
2635+ defm _VV : VPseudoBinaryM<m.vrclass, m, Commutable=Commutable>;
26472636}
26482637
2649- multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f, bits<2> TargetConstraintType = 1> {
2650- defm "_V" # f.FX :
2651- VPseudoBinaryM<VR, m.vrclass, f.fprclass, m,
2652- !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
2638+ multiclass VPseudoBinaryM_VX<LMULInfo m> {
2639+ defm _VX : VPseudoBinaryM<GPR, m>;
26532640}
26542641
2655- multiclass VPseudoBinaryM_VI<LMULInfo m, bits<2> TargetConstraintType = 1> {
2656- defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
2657- !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
2642+ multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f> {
2643+ defm "_V" # f.FX : VPseudoBinaryM<f.fprclass, m>;
2644+ }
2645+
2646+ multiclass VPseudoBinaryM_VI<LMULInfo m> {
2647+ defm _VI : VPseudoBinaryM<simm5, m>;
26582648}
26592649
26602650multiclass VPseudoVGTR_VV_VX_VI {
@@ -3397,34 +3387,44 @@ multiclass VPseudoVWMAC_VV_VF_BF_RM {
33973387multiclass VPseudoVCMPM_VV_VX_VI<bit Commutable = 0> {
33983388 foreach m = MxList in {
33993389 defvar mx = m.MX;
3400- defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2, Commutable=Commutable>,
3390+ defm "" : VPseudoBinaryM_VV<m, Commutable=Commutable>,
34013391 SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
3402- defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2 >,
3392+ defm "" : VPseudoBinaryM_VX<m>,
34033393 SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
3404- defm "" : VPseudoBinaryM_VI<m, TargetConstraintType=2 >,
3394+ defm "" : VPseudoBinaryM_VI<m>,
34053395 SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
34063396 }
34073397}
34083398
34093399multiclass VPseudoVCMPM_VV_VX {
34103400 foreach m = MxList in {
34113401 defvar mx = m.MX;
3412- defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2 >,
3402+ defm "" : VPseudoBinaryM_VV<m>,
34133403 SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
3414- defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
3404+ defm "" : VPseudoBinaryM_VX<m>,
3405+ SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
3406+ }
3407+ }
3408+
3409+ multiclass VPseudoVCMPM_VX_VI {
3410+ foreach m = MxList in {
3411+ defvar mx = m.MX;
3412+ defm "" : VPseudoBinaryM_VX<m>,
34153413 SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
3414+ defm "" : VPseudoBinaryM_VI<m>,
3415+ SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
34163416 }
34173417}
34183418
34193419multiclass VPseudoVCMPM_VV_VF {
34203420 foreach m = MxListF in {
3421- defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2 >,
3421+ defm "" : VPseudoBinaryM_VV<m>,
34223422 SchedBinary<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV", m.MX>;
34233423 }
34243424
34253425 foreach f = FPList in {
34263426 foreach m = f.MxList in {
3427- defm "" : VPseudoBinaryM_VF<m, f, TargetConstraintType=2 >,
3427+ defm "" : VPseudoBinaryM_VF<m, f>,
34283428 SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
34293429 }
34303430 }
@@ -3433,22 +3433,12 @@ multiclass VPseudoVCMPM_VV_VF {
34333433multiclass VPseudoVCMPM_VF {
34343434 foreach f = FPList in {
34353435 foreach m = f.MxList in {
3436- defm "" : VPseudoBinaryM_VF<m, f, TargetConstraintType=2 >,
3436+ defm "" : VPseudoBinaryM_VF<m, f>,
34373437 SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
34383438 }
34393439 }
34403440}
34413441
3442- multiclass VPseudoVCMPM_VX_VI {
3443- foreach m = MxList in {
3444- defvar mx = m.MX;
3445- defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
3446- SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
3447- defm "" : VPseudoBinaryM_VI<m, TargetConstraintType=2>,
3448- SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
3449- }
3450- }
3451-
34523442multiclass VPseudoVRED_VS {
34533443 foreach m = MxList in {
34543444 defvar mx = m.MX;
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