[CT] switch to using class for CTSELECT_I386* and fix formatting

Author: kumarak

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -37999,8 +37999,10 @@ X86TargetLowering::emitPatchableEventCall(MachineInstr &MI,
 /// This approach ensures that when i64 is type-legalized into two i32
 /// operations, both operations share the same condition byte rather than
 /// each independently reading (and destroying) EFLAGS.
-static MachineBasicBlock *emitCTSelectI386WithConditionMaterialization(
-    MachineInstr &MI, MachineBasicBlock *BB, unsigned InternalPseudoOpcode) {
+static MachineBasicBlock *
+emitCTSelectI386WithConditionMaterialization(MachineInstr &MI,
+                                              MachineBasicBlock *BB,
+                                              unsigned InternalPseudoOpcode) {
   const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
   const MIMetadata MIMD(MI);
   MachineFunction *MF = BB->getParent();
@@ -38033,23 +38035,23 @@ static MachineBasicBlock *emitCTSelectI386WithConditionMaterialization(
   Register TmpMaskReg;
 
   // Determine the register class for tmp_mask based on the data type
-  if (InternalPseudoOpcode == X86::CTSELECT_I386_INT_GR8rr)
+  if (InternalPseudoOpcode == X86::CTSELECT_I386_INT_GR8rr) {
     TmpMaskReg = MRI.createVirtualRegister(&X86::GR8RegClass);
-  else if (InternalPseudoOpcode == X86::CTSELECT_I386_INT_GR16rr)
+  } else if (InternalPseudoOpcode == X86::CTSELECT_I386_INT_GR16rr) {
     TmpMaskReg = MRI.createVirtualRegister(&X86::GR16RegClass);
-  else if (InternalPseudoOpcode == X86::CTSELECT_I386_INT_GR32rr)
+  } else if (InternalPseudoOpcode == X86::CTSELECT_I386_INT_GR32rr) {
     TmpMaskReg = MRI.createVirtualRegister(&X86::GR32RegClass);
-  else {
+  } else {
     llvm_unreachable("Unknown internal pseudo opcode");
   }
 
   BuildMI(*BB, MI, MIMD, TII->get(InternalPseudoOpcode))
-      .addDef(DstReg)       // dst (output)
-      .addDef(TmpByteReg)   // tmp_byte (output)
-      .addDef(TmpMaskReg)   // tmp_mask (output)
-      .addReg(Src1Reg)      // src1 (input)
-      .addReg(Src2Reg)      // src2 (input)
-      .addReg(CondByteReg); // pre-materialized condition byte (input)
+      .addDef(DstReg)         // dst (output)
+      .addDef(TmpByteReg)     // tmp_byte (output)
+      .addDef(TmpMaskReg)     // tmp_mask (output)
+      .addReg(Src1Reg)        // src1 (input)
+      .addReg(Src2Reg)        // src2 (input)
+      .addReg(CondByteReg);   // pre-materialized condition byte (input)
 
   MI.eraseFromParent();
   return BB;

llvm/lib/Target/X86/X86InstrCompiler.td

@@ -702,43 +702,45 @@ def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
 let isPseudo = 1, isNotDuplicable = 1 in {
   // Phase 1: Initial pseudos that consume EFLAGS (via custom inserter)
   // These are matched by patterns and convert EFLAGS to condition byte
-  multiclass CTSELECT_I386_INITIAL<RegisterClass RC, ValueType VT> {
-    let Uses = [EFLAGS], Defs = [EFLAGS], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
-      def rr : PseudoI<(outs RC:$dst),
-                       (ins RC:$src1, RC:$src2, i8imm:$cond), 
-                       [(set RC:$dst, (VT(X86ctselect RC:$src1, RC:$src2, timm:$cond, EFLAGS)))]>;
-    }
+  class CTSELECT_I386_INITIAL<RegisterClass RC, ValueType VT>
+      : PseudoI<(outs RC:$dst),
+                (ins RC:$src1, RC:$src2, i8imm:$cond),
+                [(set RC:$dst, (VT(X86ctselect RC:$src1, RC:$src2, timm:$cond,
+                                        EFLAGS)))]> {
+    let Uses = [EFLAGS];
+    let Defs = [EFLAGS];
+    let usesCustomInserter = 1;
+    let hasNoSchedulingInfo = 1;
   }
 
   // Phase 2: Internal pseudos with pre-materialized condition byte (post-RA expansion)
   // These generate the actual constant-time instruction bundles
-  multiclass CTSELECT_I386_INTERNAL<RegisterClass RC, RegisterClass ByteRC> {
-    let hasNoSchedulingInfo = 1 in {
-      def rr : PseudoI<(outs RC:$dst, ByteRC:$tmp_byte, RC:$tmp_mask),
-                       (ins RC:$src1, RC:$src2, ByteRC:$cond_byte), []> {
-        let Constraints =
-            "@earlyclobber $dst,@earlyclobber $tmp_byte,@earlyclobber "
-            "$tmp_mask";
-      }
-    }
+  class CTSELECT_I386_INTERNAL<RegisterClass RC, RegisterClass ByteRC>
+      : PseudoI<(outs RC:$dst, ByteRC:$tmp_byte, RC:$tmp_mask),
+                (ins RC:$src1, RC:$src2, ByteRC:$cond_byte), []> {
+    let hasNoSchedulingInfo = 1;
+    let Constraints = "@earlyclobber $dst,@earlyclobber $tmp_byte,@earlyclobber $tmp_mask";
   }
 }
 
 // Phase 1 pseudos for non-CMOV targets (custom inserter materializes condition)
 let isCodeGenOnly = 1, hasSideEffects = 1, ForceDisassemble = 1 in {
   let Predicates = [NoNativeCMOV] in {
-    defm CTSELECT_I386_GR8 : CTSELECT_I386_INITIAL<GR8, i8>;
-    defm CTSELECT_I386_GR16 : CTSELECT_I386_INITIAL<GR16, i16>;
-    defm CTSELECT_I386_GR32 : CTSELECT_I386_INITIAL<GR32, i32>;
+    def CTSELECT_I386_GR8rr : CTSELECT_I386_INITIAL<GR8, i8>;
+    def CTSELECT_I386_GR16rr : CTSELECT_I386_INITIAL<GR16, i16>;
+    def CTSELECT_I386_GR32rr : CTSELECT_I386_INITIAL<GR32, i32>;
   }
 }
 
 // Phase 2 pseudos (post-RA expansion with pre-materialized condition byte)
 let isCodeGenOnly = 1, hasSideEffects = 1, ForceDisassemble = 1 in {
   let Predicates = [NoNativeCMOV] in {
-    defm CTSELECT_I386_INT_GR8 : CTSELECT_I386_INTERNAL<GR8, GR8>;
-    defm CTSELECT_I386_INT_GR16 : CTSELECT_I386_INTERNAL<GR16, GR8>;
-    defm CTSELECT_I386_INT_GR32 : CTSELECT_I386_INTERNAL<GR32, GR8>;
+    def CTSELECT_I386_INT_GR8rr :
+        CTSELECT_I386_INTERNAL<GR8, GR8>;
+    def CTSELECT_I386_INT_GR16rr :
+        CTSELECT_I386_INTERNAL<GR16, GR8>;
+    def CTSELECT_I386_INT_GR32rr :
+        CTSELECT_I386_INTERNAL<GR32, GR8>;
   }
 }
 
@@ -747,12 +749,12 @@ let hasSideEffects = 1,
     Constraints = "$dst = $src1" in {
 
   let Predicates = [FPStackf32] in
-    defm CTSELECT_I386_FP32 : CTSELECT_I386_INITIAL<RFP32, f32>;
+    def CTSELECT_I386_FP32rr : CTSELECT_I386_INITIAL<RFP32, f32>;
 
   let Predicates = [FPStackf64] in
-    defm CTSELECT_I386_FP64 : CTSELECT_I386_INITIAL<RFP64, f64>;
+    def CTSELECT_I386_FP64rr : CTSELECT_I386_INITIAL<RFP64, f64>;
 
-  defm CTSELECT_I386_FP80 : CTSELECT_I386_INITIAL<RFP80, f80>;
+  def CTSELECT_I386_FP80rr : CTSELECT_I386_INITIAL<RFP80, f80>;
 }
 
 // Pattern matching for non-native-CMOV CTSELECT (routes to custom inserter for condition materialization)

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -1022,7 +1022,6 @@ bool X86InstrInfo::expandCtSelectIntWithoutCMOV(MachineInstr &MI) const {
 
   // Remove the original pseudo instruction
   MI.eraseFromParent();
-
   return true;
 }