Skip to content

Commit df09547

Browse files
committed
Change the mixed instruction from xor to sub and change interface name from xor to mix
1 parent 65acb8c commit df09547

File tree

11 files changed

+42
-38
lines changed

11 files changed

+42
-38
lines changed

llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2134,11 +2134,10 @@ class LLVM_ABI TargetLoweringBase {
21342134
/// getIRStackGuard returns nullptr.
21352135
virtual Value *getSDagStackGuard(const Module &M) const;
21362136

2137-
/// If this function returns true, stack protection checks should XOR the
2138-
/// frame pointer (or whichever pointer is used to address locals) into the
2137+
/// If this function returns true, stack protection checks should mix the
21392138
/// stack guard value before checking it. getIRStackGuard must return nullptr
21402139
/// if this returns true.
2141-
virtual bool useStackGuardXorFP() const { return false; }
2140+
virtual bool useStackGuardMixCookie() const { return false; }
21422141

21432142
/// If the target has a standard stack protection check function that
21442143
/// performs validation and error handling, returns the function. Otherwise,
@@ -5827,8 +5826,9 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
58275826
/// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
58285827
virtual bool useLoadStackGuardNode(const Module &M) const { return false; }
58295828

5830-
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
5831-
const SDLoc &DL, bool FailureBB) const {
5829+
virtual SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
5830+
const SDLoc &DL,
5831+
bool FailureBB) const {
58325832
llvm_unreachable("not implemented for this target");
58335833
}
58345834

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3963,8 +3963,9 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
39633963
MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile)
39643964
.getReg(0);
39653965

3966-
if (TLI->useStackGuardXorFP()) {
3967-
LLVM_DEBUG(dbgs() << "Stack protector xor'ing with FP not yet implemented");
3966+
if (TLI->useStackGuardMixCookie()) {
3967+
LLVM_DEBUG(
3968+
dbgs() << "Stack protector mix'ing the cookie not yet implemented");
39683969
return false;
39693970
}
39703971

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3128,8 +3128,8 @@ void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
31283128
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
31293129
MachineMemOperand::MOVolatile);
31303130

3131-
if (TLI.useStackGuardXorFP())
3132-
GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl, false);
3131+
if (TLI.useStackGuardMixCookie())
3132+
GuardVal = TLI.emitStackGuardMixCookie(DAG, GuardVal, dl, false);
31333133

31343134
// If we're using function-based instrumentation, call the guard check
31353135
// function
@@ -3237,8 +3237,8 @@ void SelectionDAGBuilder::visitSPDescriptorFailure(
32373237
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
32383238
MachineMemOperand::MOVolatile);
32393239

3240-
if (TLI.useStackGuardXorFP())
3241-
GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl, true);
3240+
if (TLI.useStackGuardMixCookie())
3241+
GuardVal = TLI.emitStackGuardMixCookie(DAG, GuardVal, dl, true);
32423242

32433243
// The target provides a guard check function to validate the guard value.
32443244
// Generate a call to that function with the content of the guard slot as
@@ -7428,8 +7428,8 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
74287428
MachinePointerInfo(Global, 0), Align,
74297429
MachineMemOperand::MOVolatile);
74307430
}
7431-
if (TLI.useStackGuardXorFP())
7432-
Res = TLI.emitStackGuardXorFP(DAG, Res, sdl, false);
7431+
if (TLI.useStackGuardMixCookie())
7432+
Res = TLI.emitStackGuardMixCookie(DAG, Res, sdl, false);
74337433
DAG.setRoot(Chain);
74347434
setValue(&I, Res);
74357435
return;

llvm/lib/CodeGen/StackProtector.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -576,7 +576,7 @@ bool InsertStackProtectors(const TargetMachine *TM, Function *F,
576576
// impossible to emit the check in IR, so the target *must* support stack
577577
// protection in SDAG.
578578
bool SupportsSelectionDAGSP =
579-
TLI->useStackGuardXorFP() ||
579+
TLI->useStackGuardMixCookie() ||
580580
(EnableSelectionDAGSP && !TM->Options.EnableFastISel);
581581
AllocaInst *AI = nullptr; // Place on stack that stores the stack guard.
582582
BasicBlock *FailBB = nullptr;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29242,18 +29242,19 @@ bool AArch64TargetLowering::useLoadStackGuardNode(const Module &M) const {
2924229242
return true;
2924329243
}
2924429244

29245-
bool AArch64TargetLowering::useStackGuardXorFP() const {
29245+
bool AArch64TargetLowering::useStackGuardMixCookie() const {
2924629246
// Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2924729247
return Subtarget->getTargetTriple().isOSMSVCRT() &&
2924829248
!getTargetMachine().Options.EnableGlobalISel;
2924929249
}
2925029250

29251-
SDValue AArch64TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG,
29252-
SDValue Val, const SDLoc &DL,
29253-
bool FailureBB) const {
29251+
SDValue AArch64TargetLowering::emitStackGuardMixCookie(SelectionDAG &DAG,
29252+
SDValue Val,
29253+
const SDLoc &DL,
29254+
bool FailureBB) const {
2925429255
if (FailureBB) {
2925529256
return DAG.getNode(
29256-
ISD::XOR, DL, Val.getValueType(), Val,
29257+
ISD::ADD, DL, Val.getValueType(), Val,
2925729258
DAG.getCopyFromReg(DAG.getEntryNode(), DL,
2925829259
getStackPointerRegisterToSaveRestore(), MVT::i64));
2925929260
}

llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -363,9 +363,10 @@ class AArch64TargetLowering : public TargetLowering {
363363
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
364364

365365
bool useLoadStackGuardNode(const Module &M) const override;
366-
bool useStackGuardXorFP() const override;
367-
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL,
368-
bool FailureBB) const override;
366+
bool useStackGuardMixCookie() const override;
367+
SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
368+
const SDLoc &DL,
369+
bool FailureBB) const override;
369370
TargetLoweringBase::LegalizeTypeAction
370371
getPreferredVectorAction(MVT VT) const override;
371372

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2502,9 +2502,9 @@ bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
25022502
!Subtarget.getTargetLowering()
25032503
->getTargetMachine()
25042504
.Options.EnableGlobalISel) {
2505-
BuildMI(MBB, MI, DL, get(AArch64::EORXrr), Reg)
2506-
.addReg(Reg, RegState::Kill)
2507-
.addReg(AArch64::SP);
2505+
BuildMI(MBB, MI, DL, get(AArch64::SUBXrr), Reg)
2506+
.addReg(AArch64::SP)
2507+
.addReg(Reg, RegState::Kill);
25082508
}
25092509

25102510
MBB.erase(MI);

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2738,14 +2738,14 @@ bool X86TargetLowering::useLoadStackGuardNode(const Module &M) const {
27382738
return Subtarget.isTargetMachO() && Subtarget.is64Bit();
27392739
}
27402740

2741-
bool X86TargetLowering::useStackGuardXorFP() const {
2741+
bool X86TargetLowering::useStackGuardMixCookie() const {
27422742
// Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
27432743
return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
27442744
}
27452745

2746-
SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
2747-
const SDLoc &DL,
2748-
bool FailureBB) const {
2746+
SDValue X86TargetLowering::emitStackGuardMixCookie(SelectionDAG &DAG,
2747+
SDValue Val, const SDLoc &DL,
2748+
bool FailureBB) const {
27492749
EVT PtrTy = getPointerTy(DAG.getDataLayout());
27502750
unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
27512751
MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);

llvm/lib/Target/X86/X86ISelLowering.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1590,10 +1590,11 @@ namespace llvm {
15901590
Value *getIRStackGuard(IRBuilderBase &IRB) const override;
15911591

15921592
bool useLoadStackGuardNode(const Module &M) const override;
1593-
bool useStackGuardXorFP() const override;
1593+
bool useStackGuardMixCookie() const override;
15941594
void insertSSPDeclarations(Module &M) const override;
1595-
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL,
1596-
bool FailureBB) const override;
1595+
SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
1596+
const SDLoc &DL,
1597+
bool FailureBB) const override;
15971598

15981599
/// Return true if the target stores SafeStack pointer at a fixed offset in
15991600
/// some non-standard address space, and populates the address space and

llvm/test/CodeGen/AArch64/mingw-refptr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -125,14 +125,14 @@ define dso_local void @sspFunc() #0 {
125125
; CHECK-NEXT: add x0, sp, #7
126126
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
127127
; CHECK-NEXT: ldr x8, [x8]
128-
; CHECK-NEXT: eor x8, x8, sp
128+
; CHECK-NEXT: sub x8, sp, x8
129129
; CHECK-NEXT: str x8, [sp, #8]
130130
; CHECK-NEXT: bl ptrUser
131131
; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
132132
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
133133
; CHECK-NEXT: ldr x9, [sp, #8]
134134
; CHECK-NEXT: ldr x8, [x8]
135-
; CHECK-NEXT: eor x8, x8, sp
135+
; CHECK-NEXT: sub x8, sp, x8
136136
; CHECK-NEXT: cmp x8, x9
137137
; CHECK-NEXT: b.ne .LBB6_2
138138
; CHECK-NEXT: // %bb.1: // %entry

0 commit comments

Comments
 (0)