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[RISCV] Use _B* suffix for vector mask logic pseudo instructions.
Replace LMUL suffixes with _B1, _B2, etc. This matches what we do for other mask only instructions like VCPOP_M, VFIRST_M, VMSBF_M, VLM, VSM, etc. Now all pseudoinstructions that use Log2SEW=0 will be consistently named.
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6 files changed

+50
-51
lines changed

6 files changed

+50
-51
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1670,7 +1670,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
16701670
: RISCV::PseudoVMSLT_VX_##suffix; \
16711671
VMSGTOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix \
16721672
: RISCV::PseudoVMSGT_VX_##suffix; \
1673-
VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix; \
1673+
VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix_b; \
16741674
VMSetOpcode = RISCV::PseudoVMSET_M_##suffix_b; \
16751675
break;
16761676
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F8, MF8, B64)
@@ -1770,13 +1770,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
17701770
VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix; \
17711771
VMOROpcode = RISCV::PseudoVMOR_MM_##suffix; \
17721772
break;
1773-
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F8, MF8)
1774-
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F4, MF4)
1775-
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F2, MF2)
1776-
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_1, M1)
1777-
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_2, M2)
1778-
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_4, M4)
1779-
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_8, M8)
1773+
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F8, B64)
1774+
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F4, B32)
1775+
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F2, B16)
1776+
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_1, B8)
1777+
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_2, B4)
1778+
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_4, B2)
1779+
CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_8, B1)
17801780
#undef CASE_VMXOR_VMANDN_VMOR_OPCODES
17811781
}
17821782
SDValue SEW = CurDAG->getTargetConstant(

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2266,11 +2266,10 @@ multiclass VPseudoBinaryV_VI_RM<Operand ImmType, LMULInfo m, string Constraint =
22662266
}
22672267

22682268
multiclass VPseudoVALU_MM<bit Commutable = 0> {
2269-
foreach m = MxList in {
2270-
defvar mx = m.MX;
2271-
let VLMul = m.value, isCommutable = Commutable in {
2272-
def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "">,
2273-
SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mx>;
2269+
foreach mti = AllMasks in {
2270+
let VLMul = mti.LMul.value, isCommutable = Commutable in {
2271+
def "_MM_" # mti.BX : VPseudoBinaryNoMask<VR, VR, VR, "">,
2272+
SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mti.LMul.MX>;
22742273
}
22752274
}
22762275
}
@@ -4943,7 +4942,7 @@ multiclass VPatBinaryV_VI_RM<string intrinsic, string instruction,
49434942
multiclass VPatBinaryM_MM<string intrinsic, string instruction> {
49444943
foreach mti = AllMasks in
49454944
let Predicates = [HasVInstructions] in
4946-
def : VPatBinaryM<intrinsic, instruction # "_MM_" # mti.LMul.MX,
4945+
def : VPatBinaryM<intrinsic, instruction # "_MM_" # mti.BX,
49474946
mti.Mask, mti.Mask, mti.Mask,
49484947
mti.Log2SEW, VR, VR>;
49494948
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1141,35 +1141,35 @@ defm : VPatAVGADD_VV_VX_RM<avgceilu, 0b00, suffix = "U">;
11411141
foreach mti = AllMasks in {
11421142
let Predicates = [HasVInstructions] in {
11431143
def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)),
1144-
(!cast<Instruction>("PseudoVMAND_MM_"#mti.LMul.MX)
1144+
(!cast<Instruction>("PseudoVMAND_MM_"#mti.BX)
11451145
VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
11461146
def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)),
1147-
(!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX)
1147+
(!cast<Instruction>("PseudoVMOR_MM_"#mti.BX)
11481148
VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
11491149
def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)),
1150-
(!cast<Instruction>("PseudoVMXOR_MM_"#mti.LMul.MX)
1150+
(!cast<Instruction>("PseudoVMXOR_MM_"#mti.BX)
11511151
VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
11521152

11531153
def : Pat<(mti.Mask (rvv_vnot (and VR:$rs1, VR:$rs2))),
1154-
(!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX)
1154+
(!cast<Instruction>("PseudoVMNAND_MM_"#mti.BX)
11551155
VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
11561156
def : Pat<(mti.Mask (rvv_vnot (or VR:$rs1, VR:$rs2))),
1157-
(!cast<Instruction>("PseudoVMNOR_MM_"#mti.LMul.MX)
1157+
(!cast<Instruction>("PseudoVMNOR_MM_"#mti.BX)
11581158
VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
11591159
def : Pat<(mti.Mask (rvv_vnot (xor VR:$rs1, VR:$rs2))),
1160-
(!cast<Instruction>("PseudoVMXNOR_MM_"#mti.LMul.MX)
1160+
(!cast<Instruction>("PseudoVMXNOR_MM_"#mti.BX)
11611161
VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
11621162

11631163
def : Pat<(mti.Mask (and VR:$rs1, (rvv_vnot VR:$rs2))),
1164-
(!cast<Instruction>("PseudoVMANDN_MM_"#mti.LMul.MX)
1164+
(!cast<Instruction>("PseudoVMANDN_MM_"#mti.BX)
11651165
VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
11661166
def : Pat<(mti.Mask (or VR:$rs1, (rvv_vnot VR:$rs2))),
1167-
(!cast<Instruction>("PseudoVMORN_MM_"#mti.LMul.MX)
1167+
(!cast<Instruction>("PseudoVMORN_MM_"#mti.BX)
11681168
VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
11691169

11701170
// Handle rvv_vnot the same as the vmnot.m pseudoinstruction.
11711171
def : Pat<(mti.Mask (rvv_vnot VR:$rs)),
1172-
(!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX)
1172+
(!cast<Instruction>("PseudoVMNAND_MM_"#mti.BX)
11731173
VR:$rs, VR:$rs, mti.AVL, mti.Log2SEW)>;
11741174
}
11751175
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2699,51 +2699,51 @@ foreach mti = AllMasks in {
26992699
(!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>;
27002700

27012701
def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)),
2702-
(!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX)
2702+
(!cast<Instruction>("PseudoVMAND_MM_" # mti.BX)
27032703
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27042704
def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)),
2705-
(!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX)
2705+
(!cast<Instruction>("PseudoVMOR_MM_" # mti.BX)
27062706
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27072707
def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)),
2708-
(!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX)
2708+
(!cast<Instruction>("PseudoVMXOR_MM_" # mti.BX)
27092709
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27102710

27112711
def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1,
27122712
(riscv_vmnot_vl VR:$rs2, VLOpFrag),
27132713
VLOpFrag)),
2714-
(!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX)
2714+
(!cast<Instruction>("PseudoVMANDN_MM_" # mti.BX)
27152715
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27162716
def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1,
27172717
(riscv_vmnot_vl VR:$rs2, VLOpFrag),
27182718
VLOpFrag)),
2719-
(!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX)
2719+
(!cast<Instruction>("PseudoVMORN_MM_" # mti.BX)
27202720
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27212721
// XOR is associative so we need 2 patterns for VMXNOR.
27222722
def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1,
27232723
VLOpFrag),
27242724
VR:$rs2, VLOpFrag)),
2725-
(!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX)
2725+
(!cast<Instruction>("PseudoVMXNOR_MM_" # mti.BX)
27262726
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27272727

27282728
def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2,
27292729
VLOpFrag),
27302730
VLOpFrag)),
2731-
(!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX)
2731+
(!cast<Instruction>("PseudoVMNAND_MM_" # mti.BX)
27322732
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27332733
def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2,
27342734
VLOpFrag),
27352735
VLOpFrag)),
2736-
(!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX)
2736+
(!cast<Instruction>("PseudoVMNOR_MM_" # mti.BX)
27372737
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27382738
def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2,
27392739
VLOpFrag),
27402740
VLOpFrag)),
2741-
(!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX)
2741+
(!cast<Instruction>("PseudoVMXNOR_MM_" # mti.BX)
27422742
VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
27432743

27442744
// Match the not idiom to the vmnot.m pseudo.
27452745
def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)),
2746-
(!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX)
2746+
(!cast<Instruction>("PseudoVMNAND_MM_" # mti.BX)
27472747
VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>;
27482748

27492749
// 15.2 Vector count population in mask vcpop.m

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -547,59 +547,59 @@ name: vmop_mm
547547
body: |
548548
bb.0:
549549
; CHECK-LABEL: name: vmop_mm
550-
; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 0 /* e8 */
551-
; CHECK-NEXT: %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 0 /* e8 */
552-
%x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
553-
%y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 0
550+
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */
551+
; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */
552+
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
553+
%y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0
554554
...
555555
---
556556
name: vmop_mm_incompatible_eew
557557
body: |
558558
bb.0:
559559
; CHECK-LABEL: name: vmop_mm_incompatible_eew
560-
; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0 /* e8 */
560+
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
561561
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
562-
%x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
562+
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
563563
%y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
564564
...
565565
---
566566
name: vmop_mm_incompatible_emul
567567
body: |
568568
bb.0:
569569
; CHECK-LABEL: name: vmop_mm_incompatible_emul
570-
; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0 /* e8 */
571-
; CHECK-NEXT: %y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 0 /* e8 */
572-
%x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
573-
%y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 0
570+
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
571+
; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */
572+
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
573+
%y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0
574574
...
575575
---
576576
name: vmop_mm_mask
577577
body: |
578578
bb.0:
579579
; CHECK-LABEL: name: vmop_mm_mask
580-
; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 0 /* e8 */
580+
; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */
581581
; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
582-
%x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
582+
%x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
583583
%y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
584584
...
585585
---
586586
name: vmop_mm_mask_larger_emul_user
587587
body: |
588588
bb.0:
589589
; CHECK-LABEL: name: vmop_mm_mask_larger_emul_user
590-
; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 0 /* e8 */
590+
; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */
591591
; CHECK-NEXT: %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */
592-
%x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
592+
%x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
593593
%y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0
594594
...
595595
---
596596
name: vmop_mm_mask_incompatible_emul
597597
body: |
598598
bb.0:
599599
; CHECK-LABEL: name: vmop_mm_mask_incompatible_emul
600-
; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0 /* e8 */
600+
; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
601601
; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
602-
%x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
602+
%x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
603603
%y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
604604
...
605605

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -822,7 +822,7 @@ body: |
822822
; CHECK-NEXT: bb.1:
823823
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
824824
; CHECK-NEXT: {{ $}}
825-
; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_MF8 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype
825+
; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype
826826
; CHECK-NEXT: BEQ %a, $x0, %bb.3
827827
; CHECK-NEXT: PseudoBR %bb.2
828828
; CHECK-NEXT: {{ $}}
@@ -857,7 +857,7 @@ body: |
857857
bb.1:
858858
successors: %bb.3, %bb.2
859859
860-
%mask:vr = PseudoVMANDN_MM_MF8 %t6, %t3, -1, 0
860+
%mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1, 0
861861
%t2:gpr = COPY $x0
862862
BEQ %a, %t2, %bb.3
863863
PseudoBR %bb.2

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