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[SelectionDAG] Fix incorrect fold condition in foldSetCCWithFunnelShift.
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2 files changed

+7
-2
lines changed

2 files changed

+7
-2
lines changed

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4462,7 +4462,11 @@ static SDValue foldSetCCWithFunnelShift(EVT VT, SDValue N0, SDValue N1,
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unsigned BitWidth = N0.getScalarValueSizeInBits();
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auto *ShAmtC = isConstOrConstSplat(N0.getOperand(2));
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if (!ShAmtC || ShAmtC->getAPIntValue().uge(BitWidth))
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if (!ShAmtC)
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return SDValue();
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APInt AmtVal = ShAmtC->getAPIntValue();
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if (AmtVal.uge(BitWidth) || AmtVal.isZero())
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return SDValue();
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// Canonicalize fshr as fshl to reduce pattern-matching.

llvm/test/CodeGen/AArch64/setcc-fsh.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -252,7 +252,8 @@ define i1 @fshl_or_ne_2(i32 %x, i32 %y) {
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define i1 @fshr_0_or_eq_0(i16 %x, i16 %y) {
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; CHECK-LABEL: fshr_0_or_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: tst w0, #0xffff
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%or = or i16 %x, %y
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%f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 0)

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