remove target feature

Author: shiltian

llvm/lib/Target/AMDGPU/AMDGPU.td

@@ -1473,13 +1473,6 @@ def FeatureWaitsBeforeSystemScopeStores : SubtargetFeature<
   "Target requires waits for loads and atomics before system scope stores"
 >;
 
-def FeaturePKF32Insts : SubtargetFeature<"pk-f32-insts",
-  "HasPKF32Insts",
-  "true",
-  "Has packed F32 instructions that only read 32 bits from a scalar operand "
-  "(SGPR or literal) and replicates the bits to both channels."
->;
-
 // Dummy feature used to disable assembler instructions.
 def FeatureDisable : SubtargetFeature<"",
   "FeatureDisable","true",
@@ -2152,7 +2145,6 @@ def FeatureISAVersion12_50 : FeatureSet<
    FeatureXNACK,
    FeatureClusters,
    FeatureD16Writes32BitVgpr,
-   FeaturePKF32Insts,
 ]>;
 
 def FeatureISAVersion12_51 : FeatureSet<

llvm/lib/Target/AMDGPU/GCNSubtarget.h

@@ -190,7 +190,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
   bool HasEmulatedSystemScopeAtomics = false;
   bool HasDefaultComponentBroadcast = false;
   bool HasXF32Insts = false;
-  bool HasPKF32Insts = false;
   /// The maximum number of instructions that may be placed within an S_CLAUSE,
   /// which is one greater than the maximum argument to S_CLAUSE. A value of 0
   /// indicates a lack of S_CLAUSE support.
@@ -1424,7 +1423,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
   /// \returns true if the target has packed f32 instructions that only read 32
   /// bits from a scalar operand (SGPR or literal) and replicates the bits to
   /// both channels.
-  bool hasPKF32Insts() const { return HasPKF32Insts; }
+  bool hasPKF32InstsReplicatingLow32BitsOfScalarInput() const {
+    return getGeneration() == GFX12 && GFX1250Insts;
+  }
 
   bool hasBitOp3Insts() const { return HasBitOp3Insts; }
 

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

@@ -775,7 +775,7 @@ static void appendFoldCandidate(SmallVectorImpl<FoldCandidate> &FoldList,
 // 32 bits from a scalar operand (SGPR or literal) and replicates the bits to
 // both channels.
 static bool isPKF32Instr(const GCNSubtarget *ST, MachineInstr *MI) {
-  if (!ST->hasPKF32Insts())
+  if (!ST->hasPKF32InstsReplicatingLow32BitsOfScalarInput())
     return false;
   switch (MI->getOpcode()) {
   case AMDGPU::V_PK_ADD_F32: