[AArch64][GlobalISel] Removed sqshl fallback occurring for <1 x i64> operands

GISel now places sqshl operands on floating point registers. Generated code is slightly less efficient compared to SDAG.

Author: JoshdRod

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

@@ -483,6 +483,7 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
   case Intrinsic::aarch64_neon_sqadd:
   case Intrinsic::aarch64_neon_sqsub:
   case Intrinsic::aarch64_crypto_sha1h:
+  case Intrinsic::aarch64_neon_sqshl:
   case Intrinsic::aarch64_crypto_sha1c:
   case Intrinsic::aarch64_crypto_sha1p:
   case Intrinsic::aarch64_crypto_sha1m:

llvm/test/CodeGen/AArch64/arm64-vshift.ll

@@ -2,11 +2,7 @@
 ; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
 ; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
-; CHECK-GI:       warning: Instruction selection used fallback path for sqshl1d
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshl1d_constant
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshl_scalar
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for sqshl_scalar_constant
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshl1d
+; CHECK-GI:  warning: Instruction selection used fallback path for uqshl1d
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshl1d_constant
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshl_scalar
 ; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uqshl_scalar_constant
@@ -155,37 +151,64 @@ define <1 x i64> @sqshl1d(ptr %A, ptr %B) nounwind {
 }
 
 define <1 x i64> @sqshl1d_constant(ptr %A) nounwind {
-; CHECK-LABEL: sqshl1d_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    sqshl d0, d0, #1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sqshl1d_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    ldr d0, [x0]
+; CHECK-SD-NEXT:    sqshl d0, d0, #1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sqshl1d_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #1 // =0x1
+; CHECK-GI-NEXT:    ldr d0, [x0]
+; CHECK-GI-NEXT:    fmov d1, x8
+; CHECK-GI-NEXT:    sqshl d0, d0, d1
+; CHECK-GI-NEXT:    ret
   %tmp1 = load <1 x i64>, ptr %A
   %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
   ret <1 x i64> %tmp3
 }
 
 define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: sqshl_scalar:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    ldr d1, [x1]
-; CHECK-NEXT:    sqshl d0, d0, d1
-; CHECK-NEXT:    fmov x0, d0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sqshl_scalar:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    ldr x8, [x0]
+; CHECK-SD-NEXT:    ldr x9, [x1]
+; CHECK-SD-NEXT:    fmov d0, x8
+; CHECK-SD-NEXT:    fmov d1, x9
+; CHECK-SD-NEXT:    sqshl d0, d0, d1
+; CHECK-SD-NEXT:    fmov x0, d0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sqshl_scalar:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    ldr d0, [x0]
+; CHECK-GI-NEXT:    ldr d1, [x1]
+; CHECK-GI-NEXT:    sqshl d0, d0, d1
+; CHECK-GI-NEXT:    fmov x0, d0
+; CHECK-GI-NEXT:    ret
   %tmp1 = load i64, ptr %A
   %tmp2 = load i64, ptr %B
   %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 %tmp2)
   ret i64 %tmp3
 }
 
 define i64 @sqshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: sqshl_scalar_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr d0, [x0]
-; CHECK-NEXT:    sqshl d0, d0, #1
-; CHECK-NEXT:    fmov x0, d0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sqshl_scalar_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    ldr d0, [x0]
+; CHECK-SD-NEXT:    sqshl d0, d0, #1
+; CHECK-SD-NEXT:    fmov x0, d0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sqshl_scalar_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #1 // =0x1
+; CHECK-GI-NEXT:    ldr d0, [x0]
+; CHECK-GI-NEXT:    fmov d1, x8
+; CHECK-GI-NEXT:    sqshl d0, d0, d1
+; CHECK-GI-NEXT:    fmov x0, d0
+; CHECK-GI-NEXT:    ret
   %tmp1 = load i64, ptr %A
   %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 1)
   ret i64 %tmp3
@@ -2616,7 +2639,6 @@ define <4 x i32> @neon_sshl4s_wrong_ext_constant_shift(ptr %A) nounwind {
 ; CHECK-GI-NEXT:    ret
   %tmp1 = load <4 x i8>, ptr %A
   %tmp2 = sext <4 x i8> %tmp1 to <4 x i32>
-  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
   ret <4 x i32> %tmp3
 }