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VarnikeVarnike
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Post-rebase update
1 parent 9987239 commit df5f36c

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3 files changed

+54
-32
lines changed

3 files changed

+54
-32
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1368,9 +1368,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
13681368

13691369
// Round-to-integer need custom lowering for fp16, as Promote doesn't work
13701370
// because the result type is integer.
1371-
for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT,
1372-
ISD::STRICT_LROUND, ISD::STRICT_LLROUND, ISD::STRICT_LRINT,
1373-
ISD::STRICT_LLRINT})
1371+
for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LLRINT, ISD::STRICT_LROUND,
1372+
ISD::STRICT_LLROUND, ISD::STRICT_LRINT, ISD::STRICT_LLRINT})
13741373
setOperationAction(Op, MVT::f16, Custom);
13751374

13761375
for (auto Op : {ISD::FROUND, ISD::FROUNDEVEN, ISD::FTRUNC,

‎llvm/test/CodeGen/ARM/fp-intrinsics.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,6 @@ define i32 @fptosi_f32(float %x) #0 {
7676
; CHECK-NOSP: bl __aeabi_f2iz
7777
; CHECK-NOSP: bl __aeabi_f2iz
7878
; CHECK-SP: vcvt.s32.f32
79-
; FIXME-CHECK-SP: vcvt.s32.f32
8079
define void @fptosi_f32_twice(float %arg, ptr %ptr) #0 {
8180
entry:
8281
%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %arg, metadata !"fpexcept.strict") #0

‎llvm/test/CodeGen/ARM/fp16-fullfp16.ll‎

Lines changed: 52 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -98,12 +98,18 @@ define i32 @test_fptosi_i32(ptr %p) {
9898
ret i32 %r
9999
}
100100

101-
; FIXME
102-
;define i64 @test_fptosi_i64(ptr %p) {
103-
; %a = load half, ptr %p, align 2
104-
; %r = fptosi half %a to i64
105-
; ret i64 %r
106-
;}
101+
define i64 @test_fptosi_i64(ptr %p) {
102+
; CHECK-LABEL: test_fptosi_i64:
103+
; CHECK: .save {r11, lr}
104+
; CHECK-NEXT: push {r11, lr}
105+
; CHECK-NEXT: ldrh r0, [r0]
106+
; CHECK-NEXT: vmov s0, r0
107+
; CHECK-NEXT: bl __fixhfdi
108+
; CHECK-NEXT: pop {r11, pc}
109+
%a = load half, ptr %p, align 2
110+
%r = fptosi half %a to i64
111+
ret i64 %r
112+
}
107113

108114
define i32 @test_fptoui_i32(ptr %p) {
109115
; CHECK-LABEL: test_fptoui_i32:
@@ -116,12 +122,18 @@ define i32 @test_fptoui_i32(ptr %p) {
116122
ret i32 %r
117123
}
118124

119-
; FIXME
120-
;define i64 @test_fptoui_i64(ptr %p) {
121-
; %a = load half, ptr %p, align 2
122-
; %r = fptoui half %a to i64
123-
; ret i64 %r
124-
;}
125+
define i64 @test_fptoui_i64(ptr %p) {
126+
; CHECK-LABEL: test_fptoui_i64:
127+
; CHECK: .save {r11, lr}
128+
; CHECK-NEXT: push {r11, lr}
129+
; CHECK-NEXT: ldrh r0, [r0]
130+
; CHECK-NEXT: vmov s0, r0
131+
; CHECK-NEXT: bl __fixunshfdi
132+
; CHECK-NEXT: pop {r11, pc}
133+
%a = load half, ptr %p, align 2
134+
%r = fptoui half %a to i64
135+
ret i64 %r
136+
}
125137

126138
define void @test_sitofp_i32(i32 %a, ptr %p) {
127139
; CHECK-LABEL: test_sitofp_i32:
@@ -145,19 +157,31 @@ define void @test_uitofp_i32(i32 %a, ptr %p) {
145157
ret void
146158
}
147159

148-
; FIXME
149-
;define void @test_sitofp_i64(i64 %a, ptr %p) {
150-
; %r = sitofp i64 %a to half
151-
; store half %r, ptr %p
152-
; ret void
153-
;}
160+
define void @test_sitofp_i64(i64 %a, ptr %p) {
161+
; CHECK-LABEL: test_sitofp_i64:
162+
; CHECK: .save {r4, lr}
163+
; CHECK-NEXT: push {r4, lr}
164+
; CHECK-NEXT: mov r4, r2
165+
; CHECK-NEXT: bl __floatdihf
166+
; CHECK-NEXT: vstr.16 s0, [r4]
167+
; CHECK-NEXT: pop {r4, pc}
168+
%r = sitofp i64 %a to half
169+
store half %r, ptr %p
170+
ret void
171+
}
154172

155-
; FIXME
156-
;define void @test_uitofp_i64(i64 %a, ptr %p) {
157-
; %r = uitofp i64 %a to half
158-
; store half %r, ptr %p
159-
; ret void
160-
;}
173+
define void @test_uitofp_i64(i64 %a, ptr %p) {
174+
; CHECK-LABEL: test_uitofp_i64:
175+
; CHECK: .save {r4, lr}
176+
; CHECK-NEXT: push {r4, lr}
177+
; CHECK-NEXT: mov r4, r2
178+
; CHECK-NEXT: bl __floatundihf
179+
; CHECK-NEXT: vstr.16 s0, [r4]
180+
; CHECK-NEXT: pop {r4, pc}
181+
%r = uitofp i64 %a to half
182+
store half %r, ptr %p
183+
ret void
184+
}
161185

162186
define void @test_fptrunc_float(float %f, ptr %p) {
163187
; CHECK-LABEL: test_fptrunc_float:
@@ -729,14 +753,14 @@ define half @sitofp_f16_i32(i32 %x) #0 {
729753
; CHECK-NEXT: movt r1, #17200
730754
; CHECK-NEXT: str r0, [sp]
731755
; CHECK-NEXT: str r1, [sp, #4]
732-
; CHECK-NEXT: vldr d16, .LCPI53_0
756+
; CHECK-NEXT: vldr d16, .LCPI57_0
733757
; CHECK-NEXT: vldr d17, [sp]
734758
; CHECK-NEXT: vsub.f64 d16, d17, d16
735759
; CHECK-NEXT: vcvtb.f16.f64 s0, d16
736760
; CHECK-NEXT: add sp, sp, #8
737761
; CHECK-NEXT: bx lr
738762
; CHECK-NEXT: .p2align 3
739-
; CHECK-NEXT: .LCPI53_0:
763+
; CHECK-NEXT: .LCPI57_0:
740764
; CHECK-NEXT: .long 2147483648
741765
; CHECK-NEXT: .long 1127219200
742766
%val = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
@@ -750,15 +774,15 @@ define half @uitofp_f16_i32(i32 %x) #0 {
750774
; CHECK-NEXT: movw r1, #0
751775
; CHECK-NEXT: str r0, [sp]
752776
; CHECK-NEXT: movt r1, #17200
753-
; CHECK-NEXT: vldr d16, .LCPI54_0
777+
; CHECK-NEXT: vldr d16, .LCPI58_0
754778
; CHECK-NEXT: str r1, [sp, #4]
755779
; CHECK-NEXT: vldr d17, [sp]
756780
; CHECK-NEXT: vsub.f64 d16, d17, d16
757781
; CHECK-NEXT: vcvtb.f16.f64 s0, d16
758782
; CHECK-NEXT: add sp, sp, #8
759783
; CHECK-NEXT: bx lr
760784
; CHECK-NEXT: .p2align 3
761-
; CHECK-NEXT: .LCPI54_0:
785+
; CHECK-NEXT: .LCPI58_0:
762786
; CHECK-NEXT: .long 0
763787
; CHECK-NEXT: .long 1127219200
764788
%val = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0

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