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[LoongArch][NFC] Add tests for vector type orn/andn (#158525)
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‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @andn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: andn_v32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
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%v1 = load <32 x i8>, ptr %a1
17+
%v2 = xor <32 x i8> %v0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%v3 = and <32 x i8> %v2, %v1
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store <32 x i8> %v3, ptr %res
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ret void
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}
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define void @andn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: andn_v16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvrepli.b $xr2, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i16>, ptr %a0
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%v1 = load <16 x i16>, ptr %a1
36+
%v2 = xor <16 x i16> %v0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
37+
%v3 = and <16 x i16> %v2, %v1
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store <16 x i16> %v3, ptr %res
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ret void
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}
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define void @andn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: andn_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvrepli.b $xr2, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = load <8 x i32>, ptr %a1
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%v2 = xor <8 x i32> %v0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%v3 = and <8 x i32> %v2, %v1
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store <8 x i32> %v3, ptr %res
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ret void
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}
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define void @andn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: andn_v4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvrepli.b $xr2, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = load <4 x i64>, ptr %a1
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%v2 = xor <4 x i64> %v0, <i64 -1, i64 -1, i64 -1, i64 -1>
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%v3 = and <4 x i64> %v2, %v1
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store <4 x i64> %v3, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @orn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: orn_v32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
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; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
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%v1 = load <32 x i8>, ptr %a1
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%v2 = xor <32 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%v3 = or <32 x i8> %v0, %v2
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store <32 x i8> %v3, ptr %res
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ret void
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}
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define void @orn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: orn_v16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvrepli.b $xr2, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
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; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i16>, ptr %a0
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%v1 = load <16 x i16>, ptr %a1
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%v2 = xor <16 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%v3 = or <16 x i16> %v0, %v2
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store <16 x i16> %v3, ptr %res
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ret void
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}
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define void @orn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: orn_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvrepli.b $xr2, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
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; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = load <8 x i32>, ptr %a1
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%v2 = xor <8 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%v3 = or <8 x i32> %v0, %v2
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store <8 x i32> %v3, ptr %res
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ret void
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}
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define void @orn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: orn_v4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a2, 0
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvrepli.b $xr2, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr2
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; CHECK-NEXT: xvor.v $xr0, $xr1, $xr0
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = load <4 x i64>, ptr %a1
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%v2 = xor <4 x i64> %v1, <i64 -1, i64 -1, i64 -1, i64 -1>
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%v3 = or <4 x i64> %v0, %v2
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store <4 x i64> %v3, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @andn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: andn_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vxori.b $vr0, $vr0, 255
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; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = xor <16 x i8> %v0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%v3 = and <16 x i8> %v2, %v1
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store <16 x i8> %v3, ptr %res
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ret void
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}
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define void @andn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: andn_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vrepli.b $vr2, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = xor <8 x i16> %v0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%v3 = and <8 x i16> %v2, %v1
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store <8 x i16> %v3, ptr %res
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ret void
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}
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define void @andn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: andn_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vrepli.b $vr2, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = xor <4 x i32> %v0, <i32 -1, i32 -1, i32 -1, i32 -1>
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%v3 = and <4 x i32> %v2, %v1
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store <4 x i32> %v3, ptr %res
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ret void
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}
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define void @andn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: andn_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vrepli.b $vr2, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = xor <2 x i64> %v0, <i64 -1, i64 -1>
75+
%v3 = and <2 x i64> %v2, %v1
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store <2 x i64> %v3, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
3+
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
4+
5+
define void @orn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
6+
; CHECK-LABEL: orn_v16i8:
7+
; CHECK: # %bb.0: # %entry
8+
; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vxori.b $vr0, $vr0, 255
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; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
15+
%v0 = load <16 x i8>, ptr %a0
16+
%v1 = load <16 x i8>, ptr %a1
17+
%v2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
18+
%v3 = or <16 x i8> %v0, %v2
19+
store <16 x i8> %v3, ptr %res
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ret void
21+
}
22+
23+
define void @orn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
24+
; CHECK-LABEL: orn_v8i16:
25+
; CHECK: # %bb.0: # %entry
26+
; CHECK-NEXT: vld $vr0, $a2, 0
27+
; CHECK-NEXT: vld $vr1, $a1, 0
28+
; CHECK-NEXT: vrepli.b $vr2, -1
29+
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
30+
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
31+
; CHECK-NEXT: vst $vr0, $a0, 0
32+
; CHECK-NEXT: ret
33+
entry:
34+
%v0 = load <8 x i16>, ptr %a0
35+
%v1 = load <8 x i16>, ptr %a1
36+
%v2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
37+
%v3 = or <8 x i16> %v0, %v2
38+
store <8 x i16> %v3, ptr %res
39+
ret void
40+
}
41+
42+
define void @orn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
43+
; CHECK-LABEL: orn_v4i32:
44+
; CHECK: # %bb.0: # %entry
45+
; CHECK-NEXT: vld $vr0, $a2, 0
46+
; CHECK-NEXT: vld $vr1, $a1, 0
47+
; CHECK-NEXT: vrepli.b $vr2, -1
48+
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
49+
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
50+
; CHECK-NEXT: vst $vr0, $a0, 0
51+
; CHECK-NEXT: ret
52+
entry:
53+
%v0 = load <4 x i32>, ptr %a0
54+
%v1 = load <4 x i32>, ptr %a1
55+
%v2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
56+
%v3 = or <4 x i32> %v0, %v2
57+
store <4 x i32> %v3, ptr %res
58+
ret void
59+
}
60+
61+
define void @orn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
62+
; CHECK-LABEL: orn_v2i64:
63+
; CHECK: # %bb.0: # %entry
64+
; CHECK-NEXT: vld $vr0, $a2, 0
65+
; CHECK-NEXT: vld $vr1, $a1, 0
66+
; CHECK-NEXT: vrepli.b $vr2, -1
67+
; CHECK-NEXT: vxor.v $vr0, $vr0, $vr2
68+
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
69+
; CHECK-NEXT: vst $vr0, $a0, 0
70+
; CHECK-NEXT: ret
71+
entry:
72+
%v0 = load <2 x i64>, ptr %a0
73+
%v1 = load <2 x i64>, ptr %a1
74+
%v2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
75+
%v3 = or <2 x i64> %v0, %v2
76+
store <2 x i64> %v3, ptr %res
77+
ret void
78+
}

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