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fixup: Improve fix flags and use MIPS pariable instrs only
1 parent 912c8e4 commit dfd363b

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3 files changed

+22
-22
lines changed

3 files changed

+22
-22
lines changed

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2750,21 +2750,17 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
27502750
.setMIFlags(MemI.getFlags());
27512751
}
27522752

2753+
// TODO: At the moment, MIPS introduced paring of instructions operating with
2754+
// word or double word. This should be extended with more instructions when more
2755+
// vendors support load/store pairing.
27532756
bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
27542757
switch (Opc) {
27552758
default:
27562759
return false;
2757-
case RISCV::SH:
2758-
case RISCV::LH:
2759-
case RISCV::LHU:
27602760
case RISCV::SW:
2761-
case RISCV::FSW:
2762-
case RISCV::LW:
2763-
case RISCV::FLW:
27642761
case RISCV::SD:
2765-
case RISCV::FSD:
27662762
case RISCV::LD:
2767-
case RISCV::FLD:
2763+
case RISCV::LW:
27682764
return true;
27692765
}
27702766
}

llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -151,11 +151,10 @@ bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
151151
bool RISCVLoadStoreOpt::tryConvertToLdStPair(
152152
MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
153153
unsigned PairOpc;
154-
// TODO: Handle the rest from RISCVInstrInfo::isPairableLdStInstOpc.
155154
Align RequiredAlignment;
156155
switch (First->getOpcode()) {
157156
default:
158-
return false;
157+
llvm_unreachable("Unsupported load/store instruction for pairing");
159158
case RISCV::SW:
160159
PairOpc = RISCV::MIPS_SWP;
161160
RequiredAlignment = Align(8);
@@ -178,13 +177,11 @@ bool RISCVLoadStoreOpt::tryConvertToLdStPair(
178177
const MachineMemOperand *MMO = *First->memoperands_begin();
179178
Align MMOAlign = MMO->getAlign();
180179

181-
// Only pair if alignment is exactly RequiredAlignment bytes.
182-
if (MMOAlign != RequiredAlignment)
180+
if (MMOAlign < RequiredAlignment)
183181
return false;
184182

185183
int64_t Offset = First->getOperand(2).getImm();
186-
if (!isUInt<7>(Offset) ||
187-
!isAligned(Align(MMO->getSize().getValue()), Offset))
184+
if (!isUInt<7>(Offset))
188185
return false;
189186

190187
MachineInstrBuilder MIB = BuildMI(
@@ -360,11 +357,20 @@ RISCVLoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
360357
// Kill flags may become invalid when moving stores for pairing.
361358
if (I->getOperand(0).isUse()) {
362359
if (!MergeForward) {
363-
// Clear kill flags on store if moving upwards.
364-
I->getOperand(0).setIsKill(false);
365-
Paired->getOperand(0).setIsKill(false);
360+
// Check if the Paired store's source register has a kill flag and clear
361+
// it only if there are intermediate uses between I and Paired.
362+
MachineOperand &PairedRegOp = Paired->getOperand(0);
363+
if (PairedRegOp.isKill()) {
364+
for (auto It = std::next(I); It != Paired; ++It) {
365+
if (It->readsRegister(PairedRegOp.getReg(), TRI)) {
366+
PairedRegOp.setIsKill(false);
367+
break;
368+
}
369+
}
370+
}
366371
} else {
367-
// Clear kill flags of the first stores register.
372+
// Clear kill flags of the first store's register in the forward
373+
// direction.
368374
Register Reg = I->getOperand(0).getReg();
369375
for (MachineInstr &MI : make_range(std::next(I), std::next(Paired)))
370376
MI.clearRegisterKills(Reg, TRI);

llvm/test/CodeGen/RISCV/load-store-pair.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -153,8 +153,7 @@ define dso_local void @testi(i8** nocapture noundef readonly %a) local_unnamed_a
153153
; RV32I_PAIR-NEXT: .cfi_offset s3, -8
154154
; RV32I_PAIR-NEXT: .cfi_offset s4, -12
155155
; RV32I_PAIR-NEXT: .cfi_offset s5, -16
156-
; RV32I_PAIR-NEXT: lw s3, 0(a0)
157-
; RV32I_PAIR-NEXT: lw s2, 4(a0)
156+
; RV32I_PAIR-NEXT: mips.lwp s3, s2, 0(a0)
158157
; RV32I_PAIR-NEXT: mips.lwp s5, s4, 8(a0)
159158
; RV32I_PAIR-NEXT: #APP
160159
; RV32I_PAIR-NEXT: #NO_APP
@@ -182,8 +181,7 @@ define dso_local void @testi(i8** nocapture noundef readonly %a) local_unnamed_a
182181
; RV32D_PAIR-NEXT: .cfi_offset s3, -8
183182
; RV32D_PAIR-NEXT: .cfi_offset s4, -12
184183
; RV32D_PAIR-NEXT: .cfi_offset s5, -16
185-
; RV32D_PAIR-NEXT: lw s3, 0(a0)
186-
; RV32D_PAIR-NEXT: lw s2, 4(a0)
184+
; RV32D_PAIR-NEXT: mips.lwp s3, s2, 0(a0)
187185
; RV32D_PAIR-NEXT: mips.lwp s5, s4, 8(a0)
188186
; RV32D_PAIR-NEXT: #APP
189187
; RV32D_PAIR-NEXT: #NO_APP

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