fix: review

Author: woruyu

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -16365,7 +16365,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
       } else {
         unsigned SignBitsA = DAG.ComputeNumSignBits(A);
         unsigned SignBitsB = DAG.ComputeNumSignBits(B);
-        CanFold = SignBitsA >= NeededBits && SignBitsB >= NeededBits;
+        CanFold = SignBitsA > NeededBits && SignBitsB > NeededBits;
       }
 
       if (CanFold && TLI.isOperationLegal(N0.getOpcode(), VT)) {

llvm/test/CodeGen/AArch64/abd-combine.ll

@@ -19,7 +19,7 @@ define <8 x i16> @abdu_const(<8 x i16> %src1) {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4h, #1
 ; CHECK-NEXT:    mov v1.d[1], v1.d[0]
-; CHECK-NEXT:    sabd v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    uabd v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
   %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
   %sub = sub <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -33,7 +33,7 @@ define <8 x i16> @abdu_const_lhs(<8 x i16> %src1) {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4h, #1
 ; CHECK-NEXT:    mov v1.d[1], v1.d[0]
-; CHECK-NEXT:    sabd v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    uabd v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
   %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
   %sub = sub <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %zextsrc1
@@ -45,10 +45,6 @@ define <8 x i16> @abdu_const_lhs(<8 x i16> %src1) {
 define <8 x i16> @abdu_const_zero(<8 x i16> %src1) {
 ; CHECK-LABEL: abdu_const_zero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    abs v0.4h, v0.4h
-; CHECK-NEXT:    abs v1.4h, v1.4h
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
 ; CHECK-NEXT:    ret
   %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
   %sub = sub <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1