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[HIP][SPIRV] Enable the SPIRV backend instead of the translator through an experimental flag.
Co-authored-by: Juan Manuel Martinez Caamaño <[email protected]>
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5 files changed

+54
-11
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5 files changed

+54
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lines changed

clang/include/clang/Driver/Options.td

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@@ -5462,6 +5462,20 @@ defm wavefrontsize64 : SimpleMFlag<"wavefrontsize64",
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defm amdgpu_precise_memory_op
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: SimpleMFlag<"amdgpu-precise-memory-op", "Enable", "Disable",
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" precise memory mode (AMDGPU only)">;
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def amdgpu_use_experimental_spirv_backend
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: Flag<["-"], "amdgpu-use-experimental-spirv-backend">,
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Group<m_amdgpu_Features_Group>,
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Flags<[HelpHidden]>,
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Visibility<[ClangOption]>,
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HelpText<"Use experimental SPIRV backend for AMDGPU compilation (AMDGPU "
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"only)">;
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def no_amdgpu_use_experimental_spirv_backend
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: Flag<["-"], "no-amdgpu-use-experimental-spirv-backend">,
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Group<m_amdgpu_Features_Group>,
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Flags<[HelpHidden]>,
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Visibility<[ClangOption]>,
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HelpText<"Do not use experimental SPIRV backend for AMDGPU compilation "
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"(AMDGPU only)">;
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def munsafe_fp_atomics : Flag<["-"], "munsafe-fp-atomics">,
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Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, Alias<fatomic_ignore_denormal_mode>;

clang/lib/Driver/Driver.cpp

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@@ -995,7 +995,7 @@ inferOffloadToolchains(Compilation &C, Action::OffloadKind Kind) {
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StringRef Triple;
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if (ID == OffloadArch::AMDGCNSPIRV)
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Triple = "spirv64-amd-amdhsa";
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Triple = "spirv64v1.6-amd-amdhsa";
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else if (IsNVIDIAOffloadArch(ID))
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Triple = C.getDefaultToolChain().getTriple().isArch64Bit()
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? "nvptx64-nvidia-cuda"

clang/lib/Driver/ToolChains/HIPAMD.cpp

Lines changed: 26 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -175,15 +175,32 @@ void AMDGCN::Linker::constructLinkAndEmitSpirvCommand(
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constructLlvmLinkCommand(C, JA, Inputs, LinkedBCFile, Args);
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// Emit SPIR-V binary.
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llvm::opt::ArgStringList TrArgs{
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"--spirv-max-version=1.6",
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"--spirv-ext=+all",
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"--spirv-allow-unknown-intrinsics",
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"--spirv-lower-const-expr",
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"--spirv-preserve-auxdata",
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"--spirv-debug-info-version=nonsemantic-shader-200"};
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SPIRV::constructTranslateCommand(C, *this, JA, Output, LinkedBCFile, TrArgs);
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bool UseSPIRVBackend = Args.hasFlag(
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options::OPT_amdgpu_use_experimental_spirv_backend,
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options::OPT_no_amdgpu_use_experimental_spirv_backend, false);
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if (UseSPIRVBackend) {
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llvm::opt::ArgStringList CmdArgs;
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CmdArgs.push_back(LinkedBCFile.getFilename());
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CmdArgs.append({"-o", Output.getFilename()});
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const char *Exec =
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C.getArgs().MakeArgString(getToolChain().GetProgramPath("llc"));
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CmdArgs.push_back("-mtriple=spirv64v1.6-amd-amdhsa");
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C.addCommand(std::make_unique<Command>(JA, *this,
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ResponseFileSupport::None(), Exec,
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CmdArgs, LinkedBCFile, Output));
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} else {
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// Emit SPIR-V binary.
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llvm::opt::ArgStringList TrArgs{
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"--spirv-max-version=1.6",
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"--spirv-ext=+all",
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"--spirv-allow-unknown-intrinsics",
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"--spirv-lower-const-expr",
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"--spirv-preserve-auxdata",
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"--spirv-debug-info-version=nonsemantic-shader-200"};
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SPIRV::constructTranslateCommand(C, *this, JA, Output, LinkedBCFile,
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TrArgs);
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}
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}
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// For amdgcn the inputs of the linker job are device bitcode and output is
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@@ -0,0 +1,12 @@
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// COM: This test case validates the behavior of -amdgpu-use-experimental-spirv-backend
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// COM: Test that -amdgpu-use-experimental-spirv-backend calls llc with the SPIRV triple.
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// RUN: %clang -x hip %s --cuda-device-only --offload-arch=amdgcnspirv -amdgpu-use-experimental-spirv-backend -### 2>&1 | FileCheck %s --check-prefix=CHECK-SPIRV-BACKEND
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// CHECK-SPIRV-BACKEND: "{{.*}}llc{{.*}}" "{{-mtriple=spirv64v[0-9]+\.[0-9]+-amd-amdhsa}}"
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// COM: Test that -no-amdgpu-use-experimental-spirv-backend calls the SPIRV translator
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// COM: %clang -x hip %s --cuda-device-only --offload-arch=amdgcnspirv -no-amdgpu-use-experimental-spirv-backend -### 2>&1 | FileCheck %s --check-prefix=CHECK-SPIRV-TRANSLATOR
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// CHECK-SPIRV-TRANSLATOR: "{{.*llvm-spirv.*}}" "{{--spirv-max-version=[0-9]+\.[0-9]}}"
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// COM: Test that by default we use the translator
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// RUN: %clang -x hip %s --cuda-device-only --offload-arch=amdgcnspirv -### 2>&1 | FileCheck %s --check-prefix=CHECK-SPIRV-TRANSLATOR

clang/test/Driver/hip-phases.hip

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Original file line numberDiff line numberDiff line change
@@ -700,6 +700,6 @@
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// SPIRV-ONLY-NEXT: 9: compiler, {8}, ir, (device-hip, amdgcnspirv)
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// SPIRV-ONLY-NEXT: 10: backend, {9}, ir, (device-hip, amdgcnspirv)
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// SPIRV-ONLY-NEXT: 11: linker, {10}, image, (device-hip, amdgcnspirv)
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// SPIRV-ONLY-NEXT: 12: offload, "device-hip (spirv64-amd-amdhsa:amdgcnspirv)" {11}, image
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// SPIRV-ONLY-NEXT: 12: offload, "device-hip (spirv64v{{[0-9]+\.[0-9]+}}-amd-amdhsa:amdgcnspirv)" {11}, image
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// SPIRV-ONLY-NEXT: 13: linker, {6, 12}, hip-fatbin, (device-hip)
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// SPIRV-ONLY-NEXT: 14: offload, "device-hip (amdgcn-amd-amdhsa)" {13}, none

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