Remove brackets

AZero13 · web-flow · commit e054677618aa · 2025-11-07T14:52:16.000-05:00
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -4420,7 +4420,7 @@ MachineInstr *
 AArch64InstructionSelector::emitCMP(MachineOperand &LHS, MachineOperand &RHS,
                                     MachineIRBuilder &MIRBuilder) const {
   MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
-  bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32);
+  bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32;
   auto RC = Is32Bit ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass;
   return emitSUBS(MRI.createVirtualRegister(RC), LHS, RHS, MIRBuilder);
 }

Original file line number	Diff line number	Diff line change
`@@ -4420,7 +4420,7 @@ MachineInstr *`
`4420`	`4420`	`AArch64InstructionSelector::emitCMP(MachineOperand &LHS, MachineOperand &RHS,`
`4421`	`4421`	`MachineIRBuilder &MIRBuilder) const {`
`4422`	`4422`	`MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();`
`4423`		`- bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32);`
	`4423`	`+ bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32;`
`4424`	`4424`	`auto RC = Is32Bit ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass;`
`4425`	`4425`	`return emitSUBS(MRI.createVirtualRegister(RC), LHS, RHS, MIRBuilder);`
`4426`	`4426`	`}`