Skip to content

Commit e05e279

Browse files
egorshamshuraegorshamshura
committed
Added missed opt,
1 parent 0eb13ab commit e05e279

File tree

4 files changed

+51
-35
lines changed

4 files changed

+51
-35
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2476,6 +2476,20 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
24762476
return SelectInst::Create(Cmp, ConstantInt::getNullValue(Ty), Y);
24772477
}
24782478

2479+
// (x + y) & (2^C) -> x & 2^C when y % 2^(C+1) == 0
2480+
if (match(Op0, m_Add(m_Value(X), m_Value(Y)))) {
2481+
const APInt *PowerC;
2482+
if (match(Op1, m_Power2(PowerC)) && !PowerC->isOne()) {
2483+
KnownBits YKnown = computeKnownBits(Y, &I);
2484+
unsigned ShiftAmount = PowerC->logBase2() + 1;
2485+
2486+
APInt YMod = YKnown.Zero;
2487+
if (YMod.getLoBits(ShiftAmount).isZero()) {
2488+
return BinaryOperator::CreateAnd(X, Op1);
2489+
}
2490+
}
2491+
}
2492+
24792493
// Canonicalize:
24802494
// (X +/- Y) & Y --> ~X & Y when Y is a power of 2.
24812495
if (match(&I, m_c_And(m_Value(Y), m_OneUse(m_CombineOr(

‎llvm/test/Transforms/InstCombine/redundant-sum-in-and.ll‎

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,8 @@ define i1 @addition_and_bitwise1(ptr %0) {
66
; CHECK-SAME: ptr [[TMP0:%.*]]) {
77
; CHECK-NEXT: [[V0:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
88
; CHECK-NEXT: [[V1:%.*]] = load i32, ptr [[V0]], align 4
9-
; CHECK-NEXT: [[V2:%.*]] = zext i32 [[V1]] to i64
10-
; CHECK-NEXT: [[V3:%.*]] = ptrtoint ptr [[V0]] to i64
11-
; CHECK-NEXT: [[V4:%.*]] = add i64 [[V2]], [[V3]]
12-
; CHECK-NEXT: [[V5:%.*]] = and i64 [[V4]], 2
13-
; CHECK-NEXT: [[V6:%.*]] = icmp eq i64 [[V5]], 0
9+
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[V1]], 2
10+
; CHECK-NEXT: [[V6:%.*]] = icmp eq i32 [[TMP2]], 0
1411
; CHECK-NEXT: ret i1 [[V6]]
1512
;
1613
%v0 = getelementptr inbounds nuw i8, ptr %0, i64 4
@@ -28,11 +25,8 @@ define i1 @addition_and_bitwise2(ptr %0) {
2825
; CHECK-SAME: ptr [[TMP0:%.*]]) {
2926
; CHECK-NEXT: [[V0:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
3027
; CHECK-NEXT: [[V1:%.*]] = load i32, ptr [[V0]], align 16
31-
; CHECK-NEXT: [[V2:%.*]] = zext i32 [[V1]] to i64
32-
; CHECK-NEXT: [[V3:%.*]] = ptrtoint ptr [[V0]] to i64
33-
; CHECK-NEXT: [[V4:%.*]] = add i64 [[V2]], [[V3]]
34-
; CHECK-NEXT: [[V5:%.*]] = and i64 [[V4]], 4
35-
; CHECK-NEXT: [[V6:%.*]] = icmp eq i64 [[V5]], 0
28+
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[V1]], 4
29+
; CHECK-NEXT: [[V6:%.*]] = icmp eq i32 [[TMP2]], 0
3630
; CHECK-NEXT: ret i1 [[V6]]
3731
;
3832
%v0 = getelementptr inbounds nuw i8, ptr %0, i64 4

‎llvm/test/Transforms/InstCombine/rem-mul-shl.ll‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -903,8 +903,7 @@ define i64 @urem_shl_vscale_overlap() vscale_range(1,16) {
903903
; CHECK-LABEL: @urem_shl_vscale_overlap(
904904
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
905905
; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 10
906-
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[SHIFT]], 2047
907-
; CHECK-NEXT: [[REM:%.*]] = and i64 [[TMP1]], 1024
906+
; CHECK-NEXT: [[REM:%.*]] = and i64 [[SHIFT]], 1024
908907
; CHECK-NEXT: ret i64 [[REM]]
909908
;
910909
%vscale = call i64 @llvm.vscale.i64()
@@ -956,10 +955,7 @@ define i32 @and_add_shl_vscale_not_power2_negative() vscale_range(1,16) {
956955
; Negative test: the %sign may be 0, https://alive2.llvm.org/ce/z/WU_j4a
957956
define i32 @and_add_and (i32 %x) {
958957
; CHECK-LABEL: @and_add_and(
959-
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 24
960-
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -2147483648
961-
; CHECK-NEXT: [[AND:%.*]] = xor i32 [[TMP2]], -2147483648
962-
; CHECK-NEXT: ret i32 [[AND]]
958+
; CHECK-NEXT: ret i32 0
963959
;
964960
%x1 = lshr i32 %x, 7
965961
%sign = and i32 %x1, 1 ; %sign = (%x >> 7) & 1

‎llvm/test/Transforms/LoopVectorize/induction.ll‎

Lines changed: 31 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1854,8 +1854,8 @@ define void @scalarize_induction_variable_04(ptr %a, ptr %p, i32 %n) {
18541854
; INTERLEAVE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[DOTIDX]]
18551855
; INTERLEAVE-NEXT: [[DOTIDX5:%.*]] = shl nsw i64 [[TMP14]], 4
18561856
; INTERLEAVE-NEXT: [[TMP19:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[DOTIDX5]]
1857-
; INTERLEAVE-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, ptr [[TMP18]], align 1
1858-
; INTERLEAVE-NEXT: [[WIDE_VEC3:%.*]] = load <16 x i32>, ptr [[TMP19]], align 1
1857+
; INTERLEAVE-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, ptr [[TMP18]], align 1, !alias.scope [[META17:![0-9]+]]
1858+
; INTERLEAVE-NEXT: [[WIDE_VEC3:%.*]] = load <16 x i32>, ptr [[TMP19]], align 1, !alias.scope [[META17]]
18591859
; INTERLEAVE-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[PAIR_I32:%.*]], ptr [[P]], i64 [[INDEX]], i32 1
18601860
; INTERLEAVE-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[PAIR_I32]], ptr [[P]], i64 [[TMP11]], i32 1
18611861
; INTERLEAVE-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[PAIR_I32]], ptr [[P]], i64 [[TMP12]], i32 1
@@ -1865,21 +1865,21 @@ define void @scalarize_induction_variable_04(ptr %a, ptr %p, i32 %n) {
18651865
; INTERLEAVE-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[PAIR_I32]], ptr [[P]], i64 [[TMP16]], i32 1
18661866
; INTERLEAVE-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[PAIR_I32]], ptr [[P]], i64 [[TMP17]], i32 1
18671867
; INTERLEAVE-NEXT: [[TMP28:%.*]] = extractelement <16 x i32> [[WIDE_VEC]], i64 0
1868-
; INTERLEAVE-NEXT: store i32 [[TMP28]], ptr [[TMP20]], align 1, !alias.scope [[META17:![0-9]+]], !noalias [[META20:![0-9]+]]
1868+
; INTERLEAVE-NEXT: store i32 [[TMP28]], ptr [[TMP20]], align 1, !alias.scope [[META20:![0-9]+]], !noalias [[META17]]
18691869
; INTERLEAVE-NEXT: [[TMP29:%.*]] = extractelement <16 x i32> [[WIDE_VEC]], i64 4
1870-
; INTERLEAVE-NEXT: store i32 [[TMP29]], ptr [[TMP21]], align 1, !alias.scope [[META17]], !noalias [[META20]]
1870+
; INTERLEAVE-NEXT: store i32 [[TMP29]], ptr [[TMP21]], align 1, !alias.scope [[META20]], !noalias [[META17]]
18711871
; INTERLEAVE-NEXT: [[TMP30:%.*]] = extractelement <16 x i32> [[WIDE_VEC]], i64 8
1872-
; INTERLEAVE-NEXT: store i32 [[TMP30]], ptr [[TMP22]], align 1, !alias.scope [[META17]], !noalias [[META20]]
1872+
; INTERLEAVE-NEXT: store i32 [[TMP30]], ptr [[TMP22]], align 1, !alias.scope [[META20]], !noalias [[META17]]
18731873
; INTERLEAVE-NEXT: [[TMP31:%.*]] = extractelement <16 x i32> [[WIDE_VEC]], i64 12
1874-
; INTERLEAVE-NEXT: store i32 [[TMP31]], ptr [[TMP23]], align 1, !alias.scope [[META17]], !noalias [[META20]]
1874+
; INTERLEAVE-NEXT: store i32 [[TMP31]], ptr [[TMP23]], align 1, !alias.scope [[META20]], !noalias [[META17]]
18751875
; INTERLEAVE-NEXT: [[TMP32:%.*]] = extractelement <16 x i32> [[WIDE_VEC3]], i64 0
1876-
; INTERLEAVE-NEXT: store i32 [[TMP32]], ptr [[TMP24]], align 1, !alias.scope [[META17]], !noalias [[META20]]
1876+
; INTERLEAVE-NEXT: store i32 [[TMP32]], ptr [[TMP24]], align 1, !alias.scope [[META20]], !noalias [[META17]]
18771877
; INTERLEAVE-NEXT: [[TMP33:%.*]] = extractelement <16 x i32> [[WIDE_VEC3]], i64 4
1878-
; INTERLEAVE-NEXT: store i32 [[TMP33]], ptr [[TMP25]], align 1, !alias.scope [[META17]], !noalias [[META20]]
1878+
; INTERLEAVE-NEXT: store i32 [[TMP33]], ptr [[TMP25]], align 1, !alias.scope [[META20]], !noalias [[META17]]
18791879
; INTERLEAVE-NEXT: [[TMP34:%.*]] = extractelement <16 x i32> [[WIDE_VEC3]], i64 8
1880-
; INTERLEAVE-NEXT: store i32 [[TMP34]], ptr [[TMP26]], align 1, !alias.scope [[META17]], !noalias [[META20]]
1880+
; INTERLEAVE-NEXT: store i32 [[TMP34]], ptr [[TMP26]], align 1, !alias.scope [[META20]], !noalias [[META17]]
18811881
; INTERLEAVE-NEXT: [[TMP35:%.*]] = extractelement <16 x i32> [[WIDE_VEC3]], i64 12
1882-
; INTERLEAVE-NEXT: store i32 [[TMP35]], ptr [[TMP27]], align 1, !alias.scope [[META17]], !noalias [[META20]]
1882+
; INTERLEAVE-NEXT: store i32 [[TMP35]], ptr [[TMP27]], align 1, !alias.scope [[META20]], !noalias [[META17]]
18831883
; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
18841884
; INTERLEAVE-NEXT: [[TMP36:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
18851885
; INTERLEAVE-NEXT: br i1 [[TMP36]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
@@ -4332,10 +4332,14 @@ define void @trunciv(ptr nocapture %a, i32 %start, i64 %k) {
43324332
; IND-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[K:%.*]], 2
43334333
; IND-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
43344334
; IND: vector.scevcheck:
4335-
; IND-NEXT: [[DOTNOT:%.*]] = icmp ult i64 [[K]], 2147483649
4336-
; IND-NEXT: br i1 [[DOTNOT]], label [[VECTOR_PH:%.*]], label [[SCALAR_PH]]
4335+
; IND-NEXT: [[TMP5:%.*]] = and i64 [[K]], 2147483648
4336+
; IND-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 0
4337+
; IND-NEXT: [[TMP7:%.*]] = add i64 [[K]], -4294967297
4338+
; IND-NEXT: [[TMP8:%.*]] = icmp ult i64 [[TMP7]], -4294967296
4339+
; IND-NEXT: [[TMP4:%.*]] = or i1 [[TMP6]], [[TMP8]]
4340+
; IND-NEXT: br i1 [[TMP4]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
43374341
; IND: vector.ph:
4338-
; IND-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 4294967294
4342+
; IND-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 6442450942
43394343
; IND-NEXT: br label [[VECTOR_BODY:%.*]]
43404344
; IND: vector.body:
43414345
; IND-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
@@ -4372,10 +4376,14 @@ define void @trunciv(ptr nocapture %a, i32 %start, i64 %k) {
43724376
; UNROLL-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[K:%.*]], 4
43734377
; UNROLL-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
43744378
; UNROLL: vector.scevcheck:
4375-
; UNROLL-NEXT: [[DOTNOT:%.*]] = icmp ult i64 [[K]], 2147483649
4376-
; UNROLL-NEXT: br i1 [[DOTNOT]], label [[VECTOR_PH:%.*]], label [[SCALAR_PH]]
4379+
; UNROLL-NEXT: [[TMP5:%.*]] = and i64 [[K]], 2147483648
4380+
; UNROLL-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 0
4381+
; UNROLL-NEXT: [[TMP7:%.*]] = add i64 [[K]], -4294967297
4382+
; UNROLL-NEXT: [[TMP8:%.*]] = icmp ult i64 [[TMP7]], -4294967296
4383+
; UNROLL-NEXT: [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP8]]
4384+
; UNROLL-NEXT: br i1 [[TMP9]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
43774385
; UNROLL: vector.ph:
4378-
; UNROLL-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 4294967292
4386+
; UNROLL-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 6442450940
43794387
; UNROLL-NEXT: br label [[VECTOR_BODY:%.*]]
43804388
; UNROLL: vector.body:
43814389
; UNROLL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
@@ -4460,10 +4468,14 @@ define void @trunciv(ptr nocapture %a, i32 %start, i64 %k) {
44604468
; INTERLEAVE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[K:%.*]], 8
44614469
; INTERLEAVE-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
44624470
; INTERLEAVE: vector.scevcheck:
4463-
; INTERLEAVE-NEXT: [[DOTNOT:%.*]] = icmp ult i64 [[K]], 2147483649
4464-
; INTERLEAVE-NEXT: br i1 [[DOTNOT]], label [[VECTOR_PH:%.*]], label [[SCALAR_PH]]
4471+
; INTERLEAVE-NEXT: [[TMP5:%.*]] = and i64 [[K]], 2147483648
4472+
; INTERLEAVE-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP5]], 0
4473+
; INTERLEAVE-NEXT: [[TMP7:%.*]] = add i64 [[K]], -4294967297
4474+
; INTERLEAVE-NEXT: [[TMP8:%.*]] = icmp ult i64 [[TMP7]], -4294967296
4475+
; INTERLEAVE-NEXT: [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP8]]
4476+
; INTERLEAVE-NEXT: br i1 [[TMP9]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
44654477
; INTERLEAVE: vector.ph:
4466-
; INTERLEAVE-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 4294967288
4478+
; INTERLEAVE-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 6442450936
44674479
; INTERLEAVE-NEXT: br label [[VECTOR_BODY:%.*]]
44684480
; INTERLEAVE: vector.body:
44694481
; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]

0 commit comments

Comments
 (0)