[LLVM][RISCV] Implement llvm.riscv.pause intrinsic

Author: imkiva

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -1886,6 +1886,12 @@ let TargetPrefix = "riscv" in {
   def int_riscv_vsm3me   : RISCVBinaryAAXUnMasked;
 } // TargetPrefix = "riscv"
 
+// Zihintpause extensions
+//===----------------------------------------------------------------------===//
+let TargetPrefix = "riscv" in {
+  def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+} // TargetPrefix = "riscv"
+
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 include "llvm/IR/IntrinsicsRISCVXTHead.td"

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -2242,6 +2242,9 @@ include "RISCVInstrInfoZclsd.td"
 // Short Forward Branch
 include "RISCVInstrInfoSFB.td"
 
+// Zihintpause extensions
+include "RISCVInstrInfoZihintpause.td"
+
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td

@@ -0,0 +1,10 @@
+//===-- RISCVInstrInfoZihintpause.td -----------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+
+let Predicates = [HasStdExtZihintpause] in {
+  def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>;
+}

llvm/test/CodeGen/RISCV/riscv-zihintpause.ll

@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RVPAUSE
+
+declare void @llvm.riscv.pause()
+
+define void @test_pause() {
+; RVPAUSE-LABEL: test_pause:
+; RVPAUSE:       # %bb.0:
+; RVPAUSE-NEXT:    pause
+; RVPAUSE-NEXT:    ret
+  call void @llvm.riscv.pause()
+  ret void
+}