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chrisjbrischrisjbris
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Respond to secon review comments - rename function and correct test
1 parent f503034 commit e073552

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2 files changed

+165
-15
lines changed

2 files changed

+165
-15
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4842,15 +4842,15 @@ AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
48424842
return SDValue();
48434843
}
48444844

4845-
static EVT IntToFloatVT(EVT VT) {
4845+
static EVT getFloatVT(EVT VT) {
48464846
return VT = VT.isVector() ? MVT::getVectorVT(MVT::getFloatingPointVT(
48474847
VT.getScalarSizeInBits()),
48484848
VT.getVectorNumElements())
48494849
: MVT::getFloatingPointVT(VT.getFixedSizeInBits());
48504850
}
48514851

4852-
static SDValue BitwiseToSrcModifierOp(SDValue N,
4853-
TargetLowering::DAGCombinerInfo &DCI) {
4852+
static SDValue getBitwiseToSrcModifierOp(SDValue N,
4853+
TargetLowering::DAGCombinerInfo &DCI) {
48544854

48554855
unsigned Opc = N.getNode()->getOpcode();
48564856
if (Opc != ISD::AND && Opc != ISD::XOR && Opc != ISD::AND)
@@ -4870,7 +4870,7 @@ static SDValue BitwiseToSrcModifierOp(SDValue N,
48704870
"Expected i32, v2i32 or i64 value type.");
48714871

48724872
uint64_t Mask = CRHS->getZExtValue();
4873-
EVT FVT = IntToFloatVT(VT);
4873+
EVT FVT = getFloatVT(VT);
48744874
SDLoc SL = SDLoc(N);
48754875
SDValue BC = DAG.getNode(ISD::BITCAST, SL, FVT, LHS);
48764876

@@ -4939,9 +4939,9 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
49394939
// Support source modifiers as integer.
49404940
// (select c, (xor/or/and x, c), y) -> (bitcast (select c)))
49414941
if (VT == MVT::i32 || VT == MVT::v2i32 || VT == MVT::i64) {
4942-
if (SDValue SrcMod = BitwiseToSrcModifierOp(True, DCI)) {
4942+
if (SDValue SrcMod = getBitwiseToSrcModifierOp(True, DCI)) {
49434943
SDLoc SL(N);
4944-
EVT FVT = IntToFloatVT(VT);
4944+
EVT FVT = getFloatVT(VT);
49454945
SDValue FRHS = DAG.getNode(ISD::BITCAST, SL, FVT, False);
49464946
SDValue FSelect = DAG.getNode(ISD::SELECT, SL, FVT, Cond, SrcMod, FRHS);
49474947
SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, FSelect);

‎llvm/test/CodeGen/AMDGPU/integer-select-source-modifiers.ll

Lines changed: 159 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s
3-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
4-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
5-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7 %s
3+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
4+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
65

76
define i32 @fneg_select_i32(i32 %cond, i32 %a, i32 %b) {
87
; GCN-LABEL: fneg_select_i32:
@@ -12,6 +11,20 @@ define i32 @fneg_select_i32(i32 %cond, i32 %a, i32 %b) {
1211
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc
1312
; GCN-NEXT: s_setpc_b64 s[30:31]
1413
;
14+
; GFX7-LABEL: fneg_select_i32:
15+
; GFX7: ; %bb.0:
16+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
17+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
18+
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc
19+
; GFX7-NEXT: s_setpc_b64 s[30:31]
20+
;
21+
; GFX9-LABEL: fneg_select_i32:
22+
; GFX9: ; %bb.0:
23+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
24+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
25+
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc
26+
; GFX9-NEXT: s_setpc_b64 s[30:31]
27+
;
1528
; GFX11-LABEL: fneg_select_i32:
1629
; GFX11: ; %bb.0:
1730
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -34,6 +47,24 @@ define <2 x i32> @fneg_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b)
3447
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc
3548
; GCN-NEXT: s_setpc_b64 s[30:31]
3649
;
50+
; GFX7-LABEL: fneg_select_v2i32:
51+
; GFX7: ; %bb.0:
52+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
53+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
54+
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, -v2, vcc
55+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
56+
; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc
57+
; GFX7-NEXT: s_setpc_b64 s[30:31]
58+
;
59+
; GFX9-LABEL: fneg_select_v2i32:
60+
; GFX9: ; %bb.0:
61+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
62+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
63+
; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, -v2, vcc
64+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
65+
; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc
66+
; GFX9-NEXT: s_setpc_b64 s[30:31]
67+
;
3768
; GFX11-LABEL: fneg_select_v2i32:
3869
; GFX11: ; %bb.0:
3970
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -56,6 +87,20 @@ define i32 @fabs_select_i32(i32 %cond, i32 %a, i32 %b) {
5687
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc
5788
; GCN-NEXT: s_setpc_b64 s[30:31]
5889
;
90+
; GFX7-LABEL: fabs_select_i32:
91+
; GFX7: ; %bb.0:
92+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
93+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
94+
; GFX7-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc
95+
; GFX7-NEXT: s_setpc_b64 s[30:31]
96+
;
97+
; GFX9-LABEL: fabs_select_i32:
98+
; GFX9: ; %bb.0:
99+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
100+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
101+
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc
102+
; GFX9-NEXT: s_setpc_b64 s[30:31]
103+
;
59104
; GFX11-LABEL: fabs_select_i32:
60105
; GFX11: ; %bb.0:
61106
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -78,6 +123,24 @@ define <2 x i32> @fabs_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b)
78123
; GCN-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc
79124
; GCN-NEXT: s_setpc_b64 s[30:31]
80125
;
126+
; GFX7-LABEL: fabs_select_v2i32:
127+
; GFX7: ; %bb.0:
128+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
129+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
130+
; GFX7-NEXT: v_cndmask_b32_e64 v0, v4, |v2|, vcc
131+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
132+
; GFX7-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc
133+
; GFX7-NEXT: s_setpc_b64 s[30:31]
134+
;
135+
; GFX9-LABEL: fabs_select_v2i32:
136+
; GFX9: ; %bb.0:
137+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
138+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
139+
; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, |v2|, vcc
140+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
141+
; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc
142+
; GFX9-NEXT: s_setpc_b64 s[30:31]
143+
;
81144
; GFX11-LABEL: fabs_select_v2i32:
82145
; GFX11: ; %bb.0:
83146
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -101,6 +164,22 @@ define i32 @fneg_fabs_select_i32(i32 %cond, i32 %a, i32 %b) {
101164
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
102165
; GCN-NEXT: s_setpc_b64 s[30:31]
103166
;
167+
; GFX7-LABEL: fneg_fabs_select_i32:
168+
; GFX7: ; %bb.0:
169+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
170+
; GFX7-NEXT: v_or_b32_e32 v1, 0x80000000, v1
171+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
172+
; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
173+
; GFX7-NEXT: s_setpc_b64 s[30:31]
174+
;
175+
; GFX9-LABEL: fneg_fabs_select_i32:
176+
; GFX9: ; %bb.0:
177+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
178+
; GFX9-NEXT: v_or_b32_e32 v1, 0x80000000, v1
179+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
180+
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
181+
; GFX9-NEXT: s_setpc_b64 s[30:31]
182+
;
104183
; GFX11-LABEL: fneg_fabs_select_i32:
105184
; GFX11: ; %bb.0:
106185
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -127,6 +206,28 @@ define <2 x i32> @fneg_fabs_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32
127206
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
128207
; GCN-NEXT: s_setpc_b64 s[30:31]
129208
;
209+
; GFX7-LABEL: fneg_fabs_select_v2i32:
210+
; GFX7: ; %bb.0:
211+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
212+
; GFX7-NEXT: v_or_b32_e32 v2, 0x80000000, v2
213+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
214+
; GFX7-NEXT: v_or_b32_e32 v3, 0x80000000, v3
215+
; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
216+
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
217+
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
218+
; GFX7-NEXT: s_setpc_b64 s[30:31]
219+
;
220+
; GFX9-LABEL: fneg_fabs_select_v2i32:
221+
; GFX9: ; %bb.0:
222+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
223+
; GFX9-NEXT: v_or_b32_e32 v2, 0x80000000, v2
224+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
225+
; GFX9-NEXT: v_or_b32_e32 v3, 0x80000000, v3
226+
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
227+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
228+
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
229+
; GFX9-NEXT: s_setpc_b64 s[30:31]
230+
;
130231
; GFX11-LABEL: fneg_fabs_select_v2i32:
131232
; GFX11: ; %bb.0:
132233
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -154,6 +255,24 @@ define i64 @fneg_select_i64(i64 %cond, i64 %a, i64 %b) {
154255
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
155256
; GCN-NEXT: s_setpc_b64 s[30:31]
156257
;
258+
; GFX7-LABEL: fneg_select_i64:
259+
; GFX7: ; %bb.0:
260+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
261+
; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
262+
; GFX7-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
263+
; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
264+
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
265+
; GFX7-NEXT: s_setpc_b64 s[30:31]
266+
;
267+
; GFX9-LABEL: fneg_select_i64:
268+
; GFX9: ; %bb.0:
269+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
270+
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
271+
; GFX9-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
272+
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
273+
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
274+
; GFX9-NEXT: s_setpc_b64 s[30:31]
275+
;
157276
; GFX11-LABEL: fneg_select_i64:
158277
; GFX11: ; %bb.0:
159278
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -178,6 +297,24 @@ define i64 @fabs_select_i64(i64 %cond, i64 %a, i64 %b) {
178297
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
179298
; GCN-NEXT: s_setpc_b64 s[30:31]
180299
;
300+
; GFX7-LABEL: fabs_select_i64:
301+
; GFX7: ; %bb.0:
302+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
303+
; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
304+
; GFX7-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
305+
; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
306+
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
307+
; GFX7-NEXT: s_setpc_b64 s[30:31]
308+
;
309+
; GFX9-LABEL: fabs_select_i64:
310+
; GFX9: ; %bb.0:
311+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
312+
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
313+
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
314+
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
315+
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
316+
; GFX9-NEXT: s_setpc_b64 s[30:31]
317+
;
181318
; GFX11-LABEL: fabs_select_i64:
182319
; GFX11: ; %bb.0:
183320
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -202,6 +339,24 @@ define i64 @fneg_fabs_select_i64(i64 %cond, i64 %a, i64 %b) {
202339
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
203340
; GCN-NEXT: s_setpc_b64 s[30:31]
204341
;
342+
; GFX7-LABEL: fneg_fabs_select_i64:
343+
; GFX7: ; %bb.0:
344+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
345+
; GFX7-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
346+
; GFX7-NEXT: v_or_b32_e32 v3, 0x80000000, v3
347+
; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
348+
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
349+
; GFX7-NEXT: s_setpc_b64 s[30:31]
350+
;
351+
; GFX9-LABEL: fneg_fabs_select_i64:
352+
; GFX9: ; %bb.0:
353+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
354+
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
355+
; GFX9-NEXT: v_or_b32_e32 v3, 0x80000000, v3
356+
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
357+
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
358+
; GFX9-NEXT: s_setpc_b64 s[30:31]
359+
;
205360
; GFX11-LABEL: fneg_fabs_select_i64:
206361
; GFX11: ; %bb.0:
207362
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -215,8 +370,3 @@ define i64 @fneg_fabs_select_i64(i64 %cond, i64 %a, i64 %b) {
215370
%select = select i1 %cmp, i64 %neg.a, i64 %b
216371
ret i64 %select
217372
}
218-
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
219-
; GFX11-FAKE16: {{.*}}
220-
; GFX11-TRUE16: {{.*}}
221-
; GFX7: {{.*}}
222-
; GFX9: {{.*}}

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