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llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include <optional>
@@ -66,6 +67,7 @@ class SIPeepholeSDWA {
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MachineInstr *createSDWAVersion(MachineInstr &MI);
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bool convertToSDWA(MachineInstr &MI, const SDWAOperandsVector &SDWAOperands);
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void legalizeScalarOperands(MachineInstr &MI, const GCNSubtarget &ST) const;
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bool strengthReduceCSelect64(MachineFunction &MF);
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public:
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bool run(MachineFunction &MF);
@@ -1362,6 +1364,40 @@ void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI,
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}
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}
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bool SIPeepholeSDWA::strengthReduceCSelect64(MachineFunction &MF) {
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF)
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for (MachineInstr &MI : make_early_inc_range(MBB)) {
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if (MI.getOpcode() != AMDGPU::S_CSELECT_B64)
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continue;
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Register Reg = MI.getOperand(0).getReg();
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MachineInstr *MustBeVCNDMASK = MRI->getOneNonDBGUser(Reg);
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if (!MustBeVCNDMASK ||
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MustBeVCNDMASK->getOpcode() != AMDGPU::V_CNDMASK_B32_e64 ||
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!MustBeVCNDMASK->getOperand(1).isImm() ||
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!MustBeVCNDMASK->getOperand(2).isImm())
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continue;
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MachineInstr *MustBeVREADFIRSTLANE =
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MRI->getOneNonDBGUser(MustBeVCNDMASK->getOperand(0).getReg());
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if (!MustBeVREADFIRSTLANE ||
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MustBeVREADFIRSTLANE->getOpcode() != AMDGPU::V_READFIRSTLANE_B32)
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continue;
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AMDGPU::S_CSELECT_B32),
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MustBeVREADFIRSTLANE->getOperand(0).getReg())
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.addImm(MI.getOperand(1).getImm())
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.addImm(MI.getOperand(2).getImm())
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.addReg(AMDGPU::SCC, RegState::Implicit);
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MustBeVREADFIRSTLANE->eraseFromParent();
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}
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return Changed;
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}
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bool SIPeepholeSDWALegacy::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
@@ -1436,6 +1472,9 @@ bool SIPeepholeSDWA::run(MachineFunction &MF) {
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} while (Changed);
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}
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// Other target-specific SSA-form peephole optimizations
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Ret |= strengthReduceCSelect64(MF);
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return Ret;
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}
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