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[SelectionDAG] Fix some SDNode type mismatches between *.td files and ISel (#117375)
This removes operands/results either in SDNode description or in ISel code so that they match each other.
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7 files changed

+15
-24
lines changed

7 files changed

+15
-24
lines changed

‎llvm/lib/Target/ARC/ARCInstrInfo.td‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -55,8 +55,7 @@ def ARCcmp : SDNode<"ARCISD::CMP", SDT_ARCcmptst, [SDNPOutGlue]>;
5555
def ARCcmov : SDNode<"ARCISD::CMOV", SDT_ARCcmov, [SDNPInGlue]>;
5656

5757
// Conditional Branch
58-
def ARCbrcc : SDNode<"ARCISD::BRcc", SDT_ARCbrcc,
59-
[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
58+
def ARCbrcc : SDNode<"ARCISD::BRcc", SDT_ARCbrcc, [SDNPHasChain, SDNPInGlue]>;
6059

6160
// Direct Call
6261
def ARCBranchLink : SDNode<"ARCISD::BL",SDT_ARCBranchLink,

‎llvm/lib/Target/AVR/AVRISelLowering.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -890,10 +890,9 @@ SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
890890
SDValue TargetCC;
891891
SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
892892

893-
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
894893
SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
895894

896-
return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
895+
return DAG.getNode(AVRISD::SELECT_CC, dl, Op.getValueType(), Ops);
897896
}
898897

899898
SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
@@ -907,10 +906,9 @@ SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
907906

908907
SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
909908
SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
910-
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
911909
SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
912910

913-
return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
911+
return DAG.getNode(AVRISD::SELECT_CC, DL, Op.getValueType(), Ops);
914912
}
915913

916914
SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {

‎llvm/lib/Target/BPF/BPFISelLowering.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -696,10 +696,9 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
696696
NegateCC(LHS, RHS, CC);
697697

698698
SDValue TargetCC = DAG.getConstant(CC, DL, LHS.getValueType());
699-
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
700699
SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
701700

702-
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
701+
return DAG.getNode(BPFISD::SELECT_CC, DL, Op.getValueType(), Ops);
703702
}
704703

705704
const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {

‎llvm/lib/Target/BPF/BPFInstrInfo.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
4444
def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
4545
[SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
4646

47-
def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
47+
def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC>;
4848
def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
4949
def BPFmemcpy : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY,
5050
[SDNPHasChain, SDNPInGlue, SDNPOutGlue,

‎llvm/lib/Target/Lanai/LanaiISelLowering.cpp‎

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -873,8 +873,7 @@ SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
873873

874874
LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
875875
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
876-
SDValue Glue =
877-
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
876+
SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);
878877

879878
return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
880879
TargetCC, Glue);
@@ -973,8 +972,7 @@ SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
973972

974973
LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
975974
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
976-
SDValue Glue =
977-
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
975+
SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);
978976

979977
return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Glue);
980978
}
@@ -990,12 +988,10 @@ SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,
990988

991989
LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
992990
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
993-
SDValue Glue =
994-
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
991+
SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);
995992

996-
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
997-
return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
998-
Glue);
993+
return DAG.getNode(LanaiISD::SELECT_CC, DL, Op.getValueType(), TrueV, FalseV,
994+
TargetCC, Glue);
999995
}
1000996

1001997
SDValue LanaiTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {

‎llvm/lib/Target/M68k/M68kISelLowering.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2399,8 +2399,8 @@ SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
23992399
// Block CopyFromReg so partial register stalls are avoided.
24002400
T1.getOpcode() != ISD::CopyFromReg &&
24012401
T2.getOpcode() != ISD::CopyFromReg) {
2402-
SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
2403-
SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
2402+
SDValue Cmov =
2403+
DAG.getNode(M68kISD::CMOV, DL, T1.getValueType(), T2, T1, CC, Cond);
24042404
return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
24052405
}
24062406
}
@@ -2418,9 +2418,8 @@ SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
24182418

24192419
// M68kISD::CMOV means set the result (which is operand 1) to the RHS if
24202420
// condition is true.
2421-
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
24222421
SDValue Ops[] = {Op2, Op1, CC, Cond};
2423-
return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
2422+
return DAG.getNode(M68kISD::CMOV, DL, Op.getValueType(), Ops);
24242423
}
24252424

24262425
/// Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes

‎llvm/lib/Target/Sparc/SparcInstrInfo.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ def SPbpicc : SDNode<"SPISD::BPICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
280280
def SPbpxcc : SDNode<"SPISD::BPXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
281281
def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
282282
def SPbrfccv9 : SDNode<"SPISD::BRFCC_V9", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
283-
def SPbrreg : SDNode<"SPISD::BR_REG", SDTSPbrreg, [SDNPHasChain, SDNPInGlue]>;
283+
def SPbrreg : SDNode<"SPISD::BR_REG", SDTSPbrreg, [SDNPHasChain]>;
284284

285285
def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
286286
def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
@@ -293,7 +293,7 @@ def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
293293
def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
294294
def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
295295
def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
296-
def SPselectreg : SDNode<"SPISD::SELECT_REG", SDTSPselectreg, [SDNPInGlue]>;
296+
def SPselectreg : SDNode<"SPISD::SELECT_REG", SDTSPselectreg>;
297297

298298
// These are target-independent nodes, but have target-specific formats.
299299
def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,

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